Details
| Original language | English |
|---|---|
| Pages (from-to) | 1-6 |
| Number of pages | 6 |
| Journal | Proceedings of SPIE - The International Society for Optical Engineering |
| Volume | 4386 |
| Publication status | Published - 26 Jul 2001 |
| Event | Photonic and Quantum Technologies for Aerospace Applications III - Orlando,FL, United States Duration: 17 Apr 2001 → 18 Apr 2001 |
Abstract
In this paper we present the HiPAR-DSP 16, a parallel and programmable processor architecture which is adapted to the demands of SAR image processing. To provide a high performance, the HiPAR-DSP 16 features an array of 16 parallel processing units. Each of these processing traits can process up to 3 instructions per clock cycle. Efficient data exchange between the processing units can be done by a shared memory with concurrent access. The HiPAR-DSP 16 is able to perform a 4096 samples complex FFT in 154 μs and a complete ωk SAR processing algorithm on 4k range line with a PRF of more than 200 Hz in real-time. This shows the high capability of the HiPAR-DSP 16 for onboard real-time SAR systems.
Keywords
- Digital signal processor (DSP), FFT processing, Real-time system, Synthetic aperture radar (SAR)
ASJC Scopus subject areas
- Materials Science(all)
- Electronic, Optical and Magnetic Materials
- Physics and Astronomy(all)
- Condensed Matter Physics
- Computer Science(all)
- Computer Science Applications
- Mathematics(all)
- Applied Mathematics
- Engineering(all)
- Electrical and Electronic Engineering
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In: Proceedings of SPIE - The International Society for Optical Engineering, Vol. 4386, 26.07.2001, p. 1-6.
Research output: Contribution to journal › Conference article › Research › peer review
}
TY - JOUR
T1 - HiPAR-DSP 16
T2 - Photonic and Quantum Technologies for Aerospace Applications III
AU - Kloos, H.
AU - Friebe, L.
AU - Wittenburg, J. P.
AU - Hinrichs, W.
AU - Lieske, H.
AU - Pirsch, P.
PY - 2001/7/26
Y1 - 2001/7/26
N2 - In this paper we present the HiPAR-DSP 16, a parallel and programmable processor architecture which is adapted to the demands of SAR image processing. To provide a high performance, the HiPAR-DSP 16 features an array of 16 parallel processing units. Each of these processing traits can process up to 3 instructions per clock cycle. Efficient data exchange between the processing units can be done by a shared memory with concurrent access. The HiPAR-DSP 16 is able to perform a 4096 samples complex FFT in 154 μs and a complete ωk SAR processing algorithm on 4k range line with a PRF of more than 200 Hz in real-time. This shows the high capability of the HiPAR-DSP 16 for onboard real-time SAR systems.
AB - In this paper we present the HiPAR-DSP 16, a parallel and programmable processor architecture which is adapted to the demands of SAR image processing. To provide a high performance, the HiPAR-DSP 16 features an array of 16 parallel processing units. Each of these processing traits can process up to 3 instructions per clock cycle. Efficient data exchange between the processing units can be done by a shared memory with concurrent access. The HiPAR-DSP 16 is able to perform a 4096 samples complex FFT in 154 μs and a complete ωk SAR processing algorithm on 4k range line with a PRF of more than 200 Hz in real-time. This shows the high capability of the HiPAR-DSP 16 for onboard real-time SAR systems.
KW - Digital signal processor (DSP)
KW - FFT processing
KW - Real-time system
KW - Synthetic aperture radar (SAR)
UR - http://www.scopus.com/inward/record.url?scp=0034774282&partnerID=8YFLogxK
U2 - 10.1117/12.434213
DO - 10.1117/12.434213
M3 - Conference article
AN - SCOPUS:0034774282
VL - 4386
SP - 1
EP - 6
JO - Proceedings of SPIE - The International Society for Optical Engineering
JF - Proceedings of SPIE - The International Society for Optical Engineering
SN - 0277-786X
Y2 - 17 April 2001 through 18 April 2001
ER -