Details
| Original language | English |
|---|---|
| Pages (from-to) | 92-96 |
| Number of pages | 5 |
| Journal | Proceedings of the Annual IEEE International ASIC Conference and Exhibit |
| Publication status | Published - 2000 |
| Event | 13th Annual IEEE International ASIC/SOC Conference - Arlington, VA, USA Duration: 13 Sept 2000 → 16 Sept 2000 |
Abstract
With the HiPAR-DSP family we present a scalable series of high performance fixed point DSPs. The HiPAR-DSP family features up to 16 SIMD controlled datapaths, where each datapath consists of a VLIW controlled set of arithmetic units (16 bit Multiply & Accumulate, 32 bit ALU and 32 bit Shift & Round). A shared on-chip memory with specially adapted parallel access is used for communication between the datapaths. The number of datapaths can easily be scaled to adapt the architecture to requirements in terms of processing power and silicon area. A flexible DMA control unit allows easy interfacing for systems on a chip. The maximum configuration of the presented DSP family can sustain a processing power of more than 3 GOPS for actual applications.
ASJC Scopus subject areas
- Engineering(all)
- Electrical and Electronic Engineering
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In: Proceedings of the Annual IEEE International ASIC Conference and Exhibit, 2000, p. 92-96.
Research output: Contribution to journal › Conference article › Research › peer review
}
TY - JOUR
T1 - HiPAR-DSP - a scalable family of high performance DSP-cores
AU - Wittenburg, Jens Peter
AU - Hinrichs, Willm
AU - Lieske, Hanno
AU - Kloos, Helge
AU - Friebe, Lars
AU - Pirsch, Peter
PY - 2000
Y1 - 2000
N2 - With the HiPAR-DSP family we present a scalable series of high performance fixed point DSPs. The HiPAR-DSP family features up to 16 SIMD controlled datapaths, where each datapath consists of a VLIW controlled set of arithmetic units (16 bit Multiply & Accumulate, 32 bit ALU and 32 bit Shift & Round). A shared on-chip memory with specially adapted parallel access is used for communication between the datapaths. The number of datapaths can easily be scaled to adapt the architecture to requirements in terms of processing power and silicon area. A flexible DMA control unit allows easy interfacing for systems on a chip. The maximum configuration of the presented DSP family can sustain a processing power of more than 3 GOPS for actual applications.
AB - With the HiPAR-DSP family we present a scalable series of high performance fixed point DSPs. The HiPAR-DSP family features up to 16 SIMD controlled datapaths, where each datapath consists of a VLIW controlled set of arithmetic units (16 bit Multiply & Accumulate, 32 bit ALU and 32 bit Shift & Round). A shared on-chip memory with specially adapted parallel access is used for communication between the datapaths. The number of datapaths can easily be scaled to adapt the architecture to requirements in terms of processing power and silicon area. A flexible DMA control unit allows easy interfacing for systems on a chip. The maximum configuration of the presented DSP family can sustain a processing power of more than 3 GOPS for actual applications.
UR - http://www.scopus.com/inward/record.url?scp=0033697024&partnerID=8YFLogxK
M3 - Conference article
AN - SCOPUS:0033697024
SP - 92
EP - 96
JO - Proceedings of the Annual IEEE International ASIC Conference and Exhibit
JF - Proceedings of the Annual IEEE International ASIC Conference and Exhibit
SN - 1063-0988
T2 - 13th Annual IEEE International ASIC/SOC Conference
Y2 - 13 September 2000 through 16 September 2000
ER -