Details
| Original language | English |
|---|---|
| Title of host publication | Lecture Notes in Computer Science |
| Subtitle of host publication | Embedded Computer Systems: Architectures, Modeling, and Simulation 23rd International Conference, SAMOS 2023 Samos, Greece, July 2–6, 2023 Proceedings |
| Editors | Cristina Silvano, Marc Reichenbach, Christian Pilato |
| Chapter | Open Hardware RISC-V Technologies |
| Pages | 255-268 |
| Number of pages | 14 |
| Volume | 23 |
| ISBN (electronic) | 978-3-031-46077-7 |
| Publication status | Published - 2023 |
Publication series
| Name | Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) |
|---|---|
| Volume | 14385 LNCS |
| ISSN (Print) | 0302-9743 |
| ISSN (electronic) | 1611-3349 |
Abstract
used in today’s high-tech drilling tools to further optimise the drilling
process. Each sensor and actuator either generates data that needs to
be processed or requires real-time input control signals. RISC-V proces-
sors are being developed to meet the computational demands of today’s
harsh environment applications. A known bottleneck for processors is
the data flow and instruction input to the processor, especially as mem-
ory response times are particularly high for the state-of-the-art 180 nm
harsh environment silicon-on-insulator (SOI) technology, further limit-
ing the design space. Therefore, this paper presents a high-performance
instruction fetch architecture that achieves a high clock frequency while
preserving high instructions per cycle. We evaluate different approaches
to implementing such a design and propose a design that is able to reach
up to 0.73 instructions per cycle (IPC) and achieve a clock frequency of
229 MHz, which is more than twice as high as previous designs in this
technology. The new architecture achieves 167 million instructions per
second (MIPS), which is four times higher than the rocket chip achieves
when synthesised for the same harsh environment technology.
Keywords
- RISC-V, Instruction Fetch, Cache, Harsh environment, ASIC, Synthesis, ASIC Synthesis, Harsh Environment
ASJC Scopus subject areas
- Mathematics(all)
- Theoretical Computer Science
- Computer Science(all)
- General Computer Science
Research Area (based on ÖFOS 2012)
- TECHNICAL SCIENCES
- Electrical Engineering, Electronics, Information Engineering
- Electrical Engineering, Electronics, Information Engineering
- Computer architecture
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Lecture Notes in Computer Science: Embedded Computer Systems: Architectures, Modeling, and Simulation 23rd International Conference, SAMOS 2023 Samos, Greece, July 2–6, 2023 Proceedings. ed. / Cristina Silvano; Marc Reichenbach; Christian Pilato. Vol. 23 2023. p. 255-268 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 14385 LNCS).
Research output: Chapter in book/report/conference proceeding › Contribution to book/anthology › Research › peer review
}
TY - CHAP
T1 - High Performance Instruction Fetch Structure within a RISC-V Processor for Use in Harsh Environments
AU - Hawich, Malte
AU - Blume, Holger
A2 - Rumpeltin, Nico
A2 - Rücker, Malte
A2 - Stuckenberg, Tobias
A2 - Silvano, Cristina
A2 - Reichenbach, Marc
A2 - Pilato, Christian
N1 - This work was founded by the German Federal Ministry for Economic Affairs and Climate Action under the grant number FKZ 020E-03EE4027. The responsibility for the content of this publication lies with the authors.
PY - 2023
Y1 - 2023
N2 - An increasing number of sensors and actuators are beingused in today’s high-tech drilling tools to further optimise the drillingprocess. Each sensor and actuator either generates data that needs tobe processed or requires real-time input control signals. RISC-V proces-sors are being developed to meet the computational demands of today’sharsh environment applications. A known bottleneck for processors isthe data flow and instruction input to the processor, especially as mem-ory response times are particularly high for the state-of-the-art 180 nmharsh environment silicon-on-insulator (SOI) technology, further limit-ing the design space. Therefore, this paper presents a high-performanceinstruction fetch architecture that achieves a high clock frequency whilepreserving high instructions per cycle. We evaluate different approachesto implementing such a design and propose a design that is able to reachup to 0.73 instructions per cycle (IPC) and achieve a clock frequency of229 MHz, which is more than twice as high as previous designs in thistechnology. The new architecture achieves 167 million instructions persecond (MIPS), which is four times higher than the rocket chip achieveswhen synthesised for the same harsh environment technology.
AB - An increasing number of sensors and actuators are beingused in today’s high-tech drilling tools to further optimise the drillingprocess. Each sensor and actuator either generates data that needs tobe processed or requires real-time input control signals. RISC-V proces-sors are being developed to meet the computational demands of today’sharsh environment applications. A known bottleneck for processors isthe data flow and instruction input to the processor, especially as mem-ory response times are particularly high for the state-of-the-art 180 nmharsh environment silicon-on-insulator (SOI) technology, further limit-ing the design space. Therefore, this paper presents a high-performanceinstruction fetch architecture that achieves a high clock frequency whilepreserving high instructions per cycle. We evaluate different approachesto implementing such a design and propose a design that is able to reachup to 0.73 instructions per cycle (IPC) and achieve a clock frequency of229 MHz, which is more than twice as high as previous designs in thistechnology. The new architecture achieves 167 million instructions persecond (MIPS), which is four times higher than the rocket chip achieveswhen synthesised for the same harsh environment technology.
KW - RISC-V
KW - Instruction Fetch
KW - Cache
KW - Harsh environment
KW - ASIC
KW - Synthesis
KW - ASIC Synthesis
KW - Harsh Environment
UR - http://www.scopus.com/inward/record.url?scp=85187705836&partnerID=8YFLogxK
U2 - 10.1007/978-3-031-46077-7_17
DO - 10.1007/978-3-031-46077-7_17
M3 - Contribution to book/anthology
SN - 978-3-031-46076-0
VL - 23
T3 - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
SP - 255
EP - 268
BT - Lecture Notes in Computer Science
ER -