TY - CHAP

T1 - High Performance Instruction Fetch Structure within a RISC-V Processor for Use in Harsh Environments

AU - Hawich, Malte

AU - Blume, Holger

A2 - Rumpeltin, Nico

A2 - Rücker, Malte

A2 - Stuckenberg, Tobias

A2 - Silvano, Cristina

A2 - Reichenbach, Marc

A2 - Pilato, Christian

N1 - This work was founded by the German Federal Ministry for Economic Affairs and Climate Action under the grant number FKZ 020E-03EE4027. The responsibility for the content of this publication lies with the authors.

PY - 2023

Y1 - 2023

N2 - An increasing number of sensors and actuators are beingused in today’s high-tech drilling tools to further optimise the drillingprocess. Each sensor and actuator either generates data that needs tobe processed or requires real-time input control signals. RISC-V proces-sors are being developed to meet the computational demands of today’sharsh environment applications. A known bottleneck for processors isthe data flow and instruction input to the processor, especially as mem-ory response times are particularly high for the state-of-the-art 180 nmharsh environment silicon-on-insulator (SOI) technology, further limit-ing the design space. Therefore, this paper presents a high-performanceinstruction fetch architecture that achieves a high clock frequency whilepreserving high instructions per cycle. We evaluate different approachesto implementing such a design and propose a design that is able to reachup to 0.73 instructions per cycle (IPC) and achieve a clock frequency of229 MHz, which is more than twice as high as previous designs in thistechnology. The new architecture achieves 167 million instructions persecond (MIPS), which is four times higher than the rocket chip achieveswhen synthesised for the same harsh environment technology.

AB - An increasing number of sensors and actuators are beingused in today’s high-tech drilling tools to further optimise the drillingprocess. Each sensor and actuator either generates data that needs tobe processed or requires real-time input control signals. RISC-V proces-sors are being developed to meet the computational demands of today’sharsh environment applications. A known bottleneck for processors isthe data flow and instruction input to the processor, especially as mem-ory response times are particularly high for the state-of-the-art 180 nmharsh environment silicon-on-insulator (SOI) technology, further limit-ing the design space. Therefore, this paper presents a high-performanceinstruction fetch architecture that achieves a high clock frequency whilepreserving high instructions per cycle. We evaluate different approachesto implementing such a design and propose a design that is able to reachup to 0.73 instructions per cycle (IPC) and achieve a clock frequency of229 MHz, which is more than twice as high as previous designs in thistechnology. The new architecture achieves 167 million instructions persecond (MIPS), which is four times higher than the rocket chip achieveswhen synthesised for the same harsh environment technology.

KW - RISC-V

KW - Instruction Fetch

KW - Cache

KW - Harsh environment

KW - ASIC

KW - Synthesis

KW - ASIC Synthesis

KW - Harsh Environment

UR - http://www.scopus.com/inward/record.url?scp=85187705836&partnerID=8YFLogxK

U2 - 10.1007/978-3-031-46077-7_17

DO - 10.1007/978-3-031-46077-7_17

M3 - Contribution to book/anthology

SN - 978-3-031-46076-0

VL - 23

T3 - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

SP - 255

EP - 268

BT - Lecture Notes in Computer Science

ER -