Details
| Original language | English |
|---|---|
| Title of host publication | Proceedings of SPIE |
| Subtitle of host publication | The International Society for Optical Engineering |
| Pages | 1076-1087 |
| Number of pages | 12 |
| Edition | pt 3 |
| Publication status | Published - 1992 |
| Event | Visual Communications and Image Processing '92 - Boston, MA, USA Duration: 18 Nov 1992 → 20 Nov 1992 |
Publication series
| Name | Proceedings of SPIE - The International Society for Optical Engineering |
|---|---|
| Number | pt 3 |
| Volume | 1818 |
| ISSN (Print) | 0277-786X |
Abstract
The architecture of a hierarchical multiprocessor (MP) system for videocoding is discussed. The topmost level of the proposed MP-system consists of identical, bus connected processing elements (PEs). A heterogeneous MIMD (multiple instruction multiple data) architecture is proposed for the PE. The PE contains a shared local memory and processing units, which are adapted to specific tasks. A strategy for optimizing the efficiency (defined by inverse area × processing time) at different levels of the hierarchy is proposed. This allows to realize an H.261 videocodec with only a few, if not a single PE. The efficiency of each PE can be increased, if multiple datablocks are processed concurrently within the PE (macropipelining). On the basis of a 1.0 μm CMOS technology a single PE (clock rate 50 MHz) can process the H.261 videocodec (except variable length coding and decoding) for CIF images at a frame rate of 18 Hz. Assuming an 0.6 μm CMOS technology, a single PE is expected to process frame rates of 30 Hz. A rough estimate of the silicon area for this technology is in the order of 100 mm2.
ASJC Scopus subject areas
- Materials Science(all)
- Electronic, Optical and Magnetic Materials
- Physics and Astronomy(all)
- Condensed Matter Physics
- Computer Science(all)
- Computer Science Applications
- Mathematics(all)
- Applied Mathematics
- Engineering(all)
- Electrical and Electronic Engineering
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Proceedings of SPIE : The International Society for Optical Engineering. pt 3. ed. 1992. p. 1076-1087 (Proceedings of SPIE - The International Society for Optical Engineering; Vol. 1818, No. pt 3).
Research output: Chapter in book/report/conference proceeding › Conference contribution › Research › peer review
}
TY - GEN
T1 - Hierarchical multiprocessor system for video signal processing
AU - Wilberg, Joerg
AU - Schoebinger, Matthias
AU - Pirsch, Peter
PY - 1992
Y1 - 1992
N2 - The architecture of a hierarchical multiprocessor (MP) system for videocoding is discussed. The topmost level of the proposed MP-system consists of identical, bus connected processing elements (PEs). A heterogeneous MIMD (multiple instruction multiple data) architecture is proposed for the PE. The PE contains a shared local memory and processing units, which are adapted to specific tasks. A strategy for optimizing the efficiency (defined by inverse area × processing time) at different levels of the hierarchy is proposed. This allows to realize an H.261 videocodec with only a few, if not a single PE. The efficiency of each PE can be increased, if multiple datablocks are processed concurrently within the PE (macropipelining). On the basis of a 1.0 μm CMOS technology a single PE (clock rate 50 MHz) can process the H.261 videocodec (except variable length coding and decoding) for CIF images at a frame rate of 18 Hz. Assuming an 0.6 μm CMOS technology, a single PE is expected to process frame rates of 30 Hz. A rough estimate of the silicon area for this technology is in the order of 100 mm2.
AB - The architecture of a hierarchical multiprocessor (MP) system for videocoding is discussed. The topmost level of the proposed MP-system consists of identical, bus connected processing elements (PEs). A heterogeneous MIMD (multiple instruction multiple data) architecture is proposed for the PE. The PE contains a shared local memory and processing units, which are adapted to specific tasks. A strategy for optimizing the efficiency (defined by inverse area × processing time) at different levels of the hierarchy is proposed. This allows to realize an H.261 videocodec with only a few, if not a single PE. The efficiency of each PE can be increased, if multiple datablocks are processed concurrently within the PE (macropipelining). On the basis of a 1.0 μm CMOS technology a single PE (clock rate 50 MHz) can process the H.261 videocodec (except variable length coding and decoding) for CIF images at a frame rate of 18 Hz. Assuming an 0.6 μm CMOS technology, a single PE is expected to process frame rates of 30 Hz. A rough estimate of the silicon area for this technology is in the order of 100 mm2.
UR - http://www.scopus.com/inward/record.url?scp=0026992398&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:0026992398
SN - 0819410187
T3 - Proceedings of SPIE - The International Society for Optical Engineering
SP - 1076
EP - 1087
BT - Proceedings of SPIE
T2 - Visual Communications and Image Processing '92
Y2 - 18 November 1992 through 20 November 1992
ER -