Details
| Original language | English |
|---|---|
| Title of host publication | Proceedings |
| Subtitle of host publication | IEEE International Symposium on Circuits and Systems |
| Pages | 1750-1753 |
| Number of pages | 4 |
| Publication status | Published - 1993 |
| Event | 1993 IEEE International Symposium on Circuits and Systems - Chicago, IL, USA Duration: 3 May 1993 → 6 May 1993 |
Publication series
| Name | Proceedings - IEEE International Symposium on Circuits and Systems |
|---|---|
| Volume | 3 |
| ISSN (Print) | 0271-4310 |
Abstract
A hierarchical multiprocessor architecture for real time video coding applications is presented. Due to the properties of actual video coding standards two strategies can be utilized for parallelization, data distribution and task distribution. To exploit the advantages of both approaches a combination of the named strategies is used in the proposed hierarchical multiprocessor architecture. For optimization of the architecture an efficiency measure is introduced which considers processing time, silicon area as well as the yield of the semiconductor process. Results are given for an implementation example.
ASJC Scopus subject areas
- Engineering(all)
- Electrical and Electronic Engineering
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Proceedings : IEEE International Symposium on Circuits and Systems. 1993. p. 1750-1753 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 3).
Research output: Chapter in book/report/conference proceeding › Conference contribution › Research › peer review
}
TY - GEN
T1 - Hierarchical multiprocessor architecture for video coding applications
AU - Pirsch, P.
AU - Gehrke, W.
AU - Hoffer, R.
PY - 1993
Y1 - 1993
N2 - A hierarchical multiprocessor architecture for real time video coding applications is presented. Due to the properties of actual video coding standards two strategies can be utilized for parallelization, data distribution and task distribution. To exploit the advantages of both approaches a combination of the named strategies is used in the proposed hierarchical multiprocessor architecture. For optimization of the architecture an efficiency measure is introduced which considers processing time, silicon area as well as the yield of the semiconductor process. Results are given for an implementation example.
AB - A hierarchical multiprocessor architecture for real time video coding applications is presented. Due to the properties of actual video coding standards two strategies can be utilized for parallelization, data distribution and task distribution. To exploit the advantages of both approaches a combination of the named strategies is used in the proposed hierarchical multiprocessor architecture. For optimization of the architecture an efficiency measure is introduced which considers processing time, silicon area as well as the yield of the semiconductor process. Results are given for an implementation example.
UR - http://www.scopus.com/inward/record.url?scp=0027289921&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:0027289921
SN - 0780312813
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
SP - 1750
EP - 1753
BT - Proceedings
T2 - 1993 IEEE International Symposium on Circuits and Systems
Y2 - 3 May 1993 through 6 May 1993
ER -