Details
| Original language | English |
|---|---|
| Title of host publication | 2009 International Symposium on Systems, Architectures, Modeling, and Simulation |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 125-132 |
| Number of pages | 8 |
| ISBN (print) | 9781424445011 |
| Publication status | Published - 16 Oct 2009 |
| Event | 2009 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, IC-SAMOS 2009 - Samos, Greece Duration: 20 Jul 2009 → 23 Jul 2009 |
Abstract
This paper presents a synchronization framework for parallel computing heterogeneous processing elements, which are controlled by a RISC processor. The communication delay between RISC and processing elements is a key issue if the RISC is not closely attached to the processing elements. Recent synchronization approaches neglect communication delays or require low communication delays. This results in a low synchronization rate between RISC and PEs. In order to overcome this delay, a special hardware-based synchronization approach is proposed that reduces the communication overhead and increases the number of executable tasks per time unit. Further, it supports parallel execution of independent hardware tasks. The approach was evaluated for a modular coprocessor architecture containing several processing elements for image processing tasks. The coarse-grained parallel execution of independent tasks significantly improves the speed of an exemplary application for aerial image based vehicle detection on straight highways.
ASJC Scopus subject areas
- Computer Science(all)
- Computational Theory and Mathematics
- Computer Science(all)
- Computer Science Applications
- Computer Science(all)
- Hardware and Architecture
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2009 International Symposium on Systems, Architectures, Modeling, and Simulation. Institute of Electrical and Electronics Engineers Inc., 2009. p. 125-132.
Research output: Chapter in book/report/conference proceeding › Conference contribution › Research › peer review
}
TY - GEN
T1 - Hardware-based synchronization framework for heterogeneous RISC/Coprocessor architectures
AU - Flatt, Holger
AU - Schmädecke, Ingo
AU - Kärgel, Michael
AU - Blume, Holger
AU - Pirsch, Peter
PY - 2009/10/16
Y1 - 2009/10/16
N2 - This paper presents a synchronization framework for parallel computing heterogeneous processing elements, which are controlled by a RISC processor. The communication delay between RISC and processing elements is a key issue if the RISC is not closely attached to the processing elements. Recent synchronization approaches neglect communication delays or require low communication delays. This results in a low synchronization rate between RISC and PEs. In order to overcome this delay, a special hardware-based synchronization approach is proposed that reduces the communication overhead and increases the number of executable tasks per time unit. Further, it supports parallel execution of independent hardware tasks. The approach was evaluated for a modular coprocessor architecture containing several processing elements for image processing tasks. The coarse-grained parallel execution of independent tasks significantly improves the speed of an exemplary application for aerial image based vehicle detection on straight highways.
AB - This paper presents a synchronization framework for parallel computing heterogeneous processing elements, which are controlled by a RISC processor. The communication delay between RISC and processing elements is a key issue if the RISC is not closely attached to the processing elements. Recent synchronization approaches neglect communication delays or require low communication delays. This results in a low synchronization rate between RISC and PEs. In order to overcome this delay, a special hardware-based synchronization approach is proposed that reduces the communication overhead and increases the number of executable tasks per time unit. Further, it supports parallel execution of independent hardware tasks. The approach was evaluated for a modular coprocessor architecture containing several processing elements for image processing tasks. The coarse-grained parallel execution of independent tasks significantly improves the speed of an exemplary application for aerial image based vehicle detection on straight highways.
UR - http://www.scopus.com/inward/record.url?scp=71949130682&partnerID=8YFLogxK
U2 - 10.1109/ICSAMOS.2009.5289223
DO - 10.1109/ICSAMOS.2009.5289223
M3 - Conference contribution
AN - SCOPUS:71949130682
SN - 9781424445011
SP - 125
EP - 132
BT - 2009 International Symposium on Systems, Architectures, Modeling, and Simulation
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2009 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, IC-SAMOS 2009
Y2 - 20 July 2009 through 23 July 2009
ER -