Hardware-assisted power estimation for design-stage processors using FPGA emulation

Sebastian Hesselbarth; Tim Baumgart; Holger Blume

doi:10.1109/PATMOS.2014.6951877

Details

Original language	English
Title of host publication	2014 24th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)
Publisher	IEEE Computer Society
ISBN (electronic)	9781479954124
Publication status	Published - 13 Nov 2014
Event	2014 International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2014 - Palma de Mallorca, Spain Duration: 29 Sept 2014 → 1 Oct 2014 Conference number: 24

ASJC Scopus subject areas

Energy(all)
Energy Engineering and Power Technology
Mathematics(all)
Modelling and Simulation

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Hardware-assisted power estimation for design-stage processors using FPGA emulation. / Hesselbarth, Sebastian; Baumgart, Tim; Blume, Holger.
2014 24th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS). IEEE Computer Society, 2014.

Research output: Chapter in book/report/conference proceeding › Conference contribution › Research › peer review

Hesselbarth, S, Baumgart, T & Blume, H 2014, Hardware-assisted power estimation for design-stage processors using FPGA emulation. in 2014 24th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS). IEEE Computer Society, 2014 International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2014, Palma de Mallorca, Spain, 29 Sept 2014. https://doi.org/10.1109/PATMOS.2014.6951877

Hesselbarth, S., Baumgart, T., & Blume, H. (2014). Hardware-assisted power estimation for design-stage processors using FPGA emulation. In 2014 24th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) IEEE Computer Society. https://doi.org/10.1109/PATMOS.2014.6951877

Hesselbarth S, Baumgart T, Blume H. Hardware-assisted power estimation for design-stage processors using FPGA emulation. In 2014 24th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS). IEEE Computer Society. 2014 doi: 10.1109/PATMOS.2014.6951877

Hesselbarth, Sebastian ; Baumgart, Tim ; Blume, Holger. / Hardware-assisted power estimation for design-stage processors using FPGA emulation. 2014 24th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS). IEEE Computer Society, 2014.

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author = "Sebastian Hesselbarth and Tim Baumgart and Holger Blume",

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N1 - Conference code: 24

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Y2 - 29 September 2014 through 1 October 2014

ER -

Research@Leibniz University

Hardware-assisted power estimation for design-stage processors using FPGA emulation

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ASJC Scopus subject areas

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