Details
| Translated title of the contribution | Hardware mapping of a video-based approach for real-time evaluation of angular histograms on a modular coprocessor architecture |
|---|---|
| Original language | German |
| Pages (from-to) | 135-142 |
| Number of pages | 8 |
| Journal | Advances in Radio Science |
| Volume | 8 |
| Publication status | Published - 1 Oct 2010 |
Abstract
This paper presents the mapping of a video-based approach for real-time evaluation of angular histograms on a modular coprocessor architecture. The architecture comprises several dedicated processing elements for parallel processing of computation-intensive image processing tasks and is coupled with a RISC processor. A configurable architecture extension, especially a processing element for evaluating angular histograms of objects in conjunction with a RISC processor, provides a real-time classification. Depending on the configuration of the architecture extension, 3 300 to 12 000 look-up tables are required for a Xilinx Virtex-5 FPGA implementation. Running at a clock frequency of 100 MHz and independently of the image resolution per frame, 100 objects of size 256 × 256 pixels are analyzed in a 25 Hz video stream by the architecture.
ASJC Scopus subject areas
- Engineering(all)
- Electrical and Electronic Engineering
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In: Advances in Radio Science, Vol. 8, 01.10.2010, p. 135-142.
Research output: Contribution to journal › Article › Research › peer review
}
TY - JOUR
T1 - Hardware-Abbildung eines videobasierten Verfahrens zur echtzeitfähigen Auswertung von Winkelhistogrammen auf eine modulare Coprozessor-Architektur
AU - Flatt, H.
AU - Tarnowsky, A.
AU - Blume, H.
AU - Pirsch, P.
PY - 2010/10/1
Y1 - 2010/10/1
N2 - This paper presents the mapping of a video-based approach for real-time evaluation of angular histograms on a modular coprocessor architecture. The architecture comprises several dedicated processing elements for parallel processing of computation-intensive image processing tasks and is coupled with a RISC processor. A configurable architecture extension, especially a processing element for evaluating angular histograms of objects in conjunction with a RISC processor, provides a real-time classification. Depending on the configuration of the architecture extension, 3 300 to 12 000 look-up tables are required for a Xilinx Virtex-5 FPGA implementation. Running at a clock frequency of 100 MHz and independently of the image resolution per frame, 100 objects of size 256 × 256 pixels are analyzed in a 25 Hz video stream by the architecture.
AB - This paper presents the mapping of a video-based approach for real-time evaluation of angular histograms on a modular coprocessor architecture. The architecture comprises several dedicated processing elements for parallel processing of computation-intensive image processing tasks and is coupled with a RISC processor. A configurable architecture extension, especially a processing element for evaluating angular histograms of objects in conjunction with a RISC processor, provides a real-time classification. Depending on the configuration of the architecture extension, 3 300 to 12 000 look-up tables are required for a Xilinx Virtex-5 FPGA implementation. Running at a clock frequency of 100 MHz and independently of the image resolution per frame, 100 objects of size 256 × 256 pixels are analyzed in a 25 Hz video stream by the architecture.
UR - http://www.scopus.com/inward/record.url?scp=77957821727&partnerID=8YFLogxK
U2 - 10.5194/ars-8-135-2010
DO - 10.5194/ars-8-135-2010
M3 - Artikel
AN - SCOPUS:77957821727
VL - 8
SP - 135
EP - 142
JO - Advances in Radio Science
JF - Advances in Radio Science
SN - 1684-9965
ER -