Details
| Original language | English |
|---|---|
| Pages | 479-488 |
| Number of pages | 10 |
| Publication status | Published - 1997 |
| Event | 1997 IEEE Workshop on Signal Processing Systems, SiPS 97: Design and Implementation - Leicester, UK Duration: 3 Nov 1997 → 5 Nov 1997 |
Conference
| Conference | 1997 IEEE Workshop on Signal Processing Systems, SiPS 97: Design and Implementation |
|---|---|
| City | Leicester, UK |
| Period | 3 Nov 1997 → 5 Nov 1997 |
Abstract
This paper describes a new architecture for content-based, interactive multimedia applications. A hardware implementation of a Java Virtual Machine (JVM) is proposed, which allows for direct execution of Java bytecode. In a single clock cycle, up to 3 bytecode instructions can be decoded and executed in parallel using a RISC pipeline. A splitable 64-bit ALU implementation addresses demanding processing requirements of typical multimedia signal processing schemes. The proposed architecture supports parallel execution of multiple Java threads. An implementation of basic building blocks of the processor with a standard-cell library provides an estimate of 150 MHz clock-speed for a 0.35 μm 3 metal layer CMOS process. With a size of less than 10 mm2 needed for the core logic, it is possible to integrate multiple JVMs together with larger cache memories on a single chip.
ASJC Scopus subject areas
- Computer Science(all)
- Signal Processing
- Engineering(all)
- Media Technology
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1997. 479-488 Paper presented at 1997 IEEE Workshop on Signal Processing Systems, SiPS 97: Design and Implementation, Leicester, UK.
Research output: Contribution to conference › Paper › Research › peer review
}
TY - CONF
T1 - Hardware realization of a Java Virtual Machine for high performance multimedia applications
AU - Berekovic, Mladen
AU - Kloos, Helge
AU - Pirsch, Peter
PY - 1997
Y1 - 1997
N2 - This paper describes a new architecture for content-based, interactive multimedia applications. A hardware implementation of a Java Virtual Machine (JVM) is proposed, which allows for direct execution of Java bytecode. In a single clock cycle, up to 3 bytecode instructions can be decoded and executed in parallel using a RISC pipeline. A splitable 64-bit ALU implementation addresses demanding processing requirements of typical multimedia signal processing schemes. The proposed architecture supports parallel execution of multiple Java threads. An implementation of basic building blocks of the processor with a standard-cell library provides an estimate of 150 MHz clock-speed for a 0.35 μm 3 metal layer CMOS process. With a size of less than 10 mm2 needed for the core logic, it is possible to integrate multiple JVMs together with larger cache memories on a single chip.
AB - This paper describes a new architecture for content-based, interactive multimedia applications. A hardware implementation of a Java Virtual Machine (JVM) is proposed, which allows for direct execution of Java bytecode. In a single clock cycle, up to 3 bytecode instructions can be decoded and executed in parallel using a RISC pipeline. A splitable 64-bit ALU implementation addresses demanding processing requirements of typical multimedia signal processing schemes. The proposed architecture supports parallel execution of multiple Java threads. An implementation of basic building blocks of the processor with a standard-cell library provides an estimate of 150 MHz clock-speed for a 0.35 μm 3 metal layer CMOS process. With a size of less than 10 mm2 needed for the core logic, it is possible to integrate multiple JVMs together with larger cache memories on a single chip.
UR - http://www.scopus.com/inward/record.url?scp=0031345396&partnerID=8YFLogxK
M3 - Paper
AN - SCOPUS:0031345396
SP - 479
EP - 488
T2 - 1997 IEEE Workshop on Signal Processing Systems, SiPS 97: Design and Implementation
Y2 - 3 November 1997 through 5 November 1997
ER -