Details
| Original language | English |
|---|---|
| Pages (from-to) | 14-25 |
| Number of pages | 12 |
| Journal | Journal of Systems Architecture |
| Volume | 77 |
| Publication status | Published - 24 Dec 2016 |
Keywords
- Methodology, Power emulation, Power estimation, Processors
ASJC Scopus subject areas
- Computer Science(all)
- Software
- Computer Science(all)
- Hardware and Architecture
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FPGA emulation methodology for fast and accurate power estimation of embedded processors. / Hesselbarth, S.; Schewior, G.; Blume, H.
In: Journal of Systems Architecture, Vol. 77, 24.12.2016, p. 14-25.
In: Journal of Systems Architecture, Vol. 77, 24.12.2016, p. 14-25.
Research output: Contribution to journal › Article › Research › peer review
Hesselbarth, S, Schewior, G & Blume, H 2016, 'FPGA emulation methodology for fast and accurate power estimation of embedded processors', Journal of Systems Architecture, vol. 77, pp. 14-25. https://doi.org/10.1016/j.sysarc.2016.12.008
Hesselbarth, S., Schewior, G., & Blume, H. (2016). FPGA emulation methodology for fast and accurate power estimation of embedded processors. Journal of Systems Architecture, 77, 14-25. https://doi.org/10.1016/j.sysarc.2016.12.008
Hesselbarth S, Schewior G, Blume H. FPGA emulation methodology for fast and accurate power estimation of embedded processors. Journal of Systems Architecture. 2016 Dec 24;77:14-25. doi: 10.1016/j.sysarc.2016.12.008
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AU - Hesselbarth, S.
AU - Schewior, G.
AU - Blume, H.
PY - 2016/12/24
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KW - Power estimation
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