Details
| Original language | English |
|---|---|
| Pages (from-to) | 120-137 |
| Number of pages | 18 |
| Journal | INTEGRATION |
| Volume | 69 |
| Early online date | 26 Feb 2019 |
| Publication status | Published - Nov 2019 |
Abstract
Keywords
- CORDIC, FPGA, Stochastic Computing, Timing analysis, Timing behavior emulation
ASJC Scopus subject areas
- Computer Science(all)
- Software
- Computer Science(all)
- Hardware and Architecture
- Engineering(all)
- Electrical and Electronic Engineering
Sustainable Development Goals
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In: INTEGRATION, Vol. 69, 11.2019, p. 120-137.
Research output: Contribution to journal › Article › Research › peer review
}
TY - JOUR
T1 - FLINT+
T2 - A runtime-configurable emulation-based stochastic timing analysis framework
AU - Weißbrich, Moritz
AU - Gerlach, Lukas
AU - Blume, Holger
AU - Najafi, A.
AU - García-Ortiz, A.
AU - Payá-Vayá, Guillermo
N1 - Funding information: This work was partly funded by the German Research Council (DFG) under project number PA 2762/1-1 .
PY - 2019/11
Y1 - 2019/11
N2 - ASICs for Stochastic Computing conditions are designed for higher energy-efficiency or performance by sacrificing computational accuracy due to intentional circuit timing violations. To optimize the stochastic behavior, iterative timing analysis campaigns have to be carried out for a variety of circuit timing corner cases. However, the application of common event-driven logic simulators usually leads to excessive analysis runtimes, increasing design time for hardware developers. In this paper, a gate-level netlist-oriented FPGA-based timing analysis framework is proposed, offering a runtime-configuration mechanism for emulating different timing corner cases in hardware without requiring multiple FPGA bitstreams. Logic gates are instrumented with a quantization-based delay model and a critical path selection algorithm is used to reduce the FPGA resource overhead. For an exemplary design space exploration of stochastic CORDIC units, speed-up factors of up to 48 for 10 ps or 476 for 100 ps timing quantization are achieved while maintaining timing behavior deviations lower than 1.5% or 4% to timing simulations, respectively.
AB - ASICs for Stochastic Computing conditions are designed for higher energy-efficiency or performance by sacrificing computational accuracy due to intentional circuit timing violations. To optimize the stochastic behavior, iterative timing analysis campaigns have to be carried out for a variety of circuit timing corner cases. However, the application of common event-driven logic simulators usually leads to excessive analysis runtimes, increasing design time for hardware developers. In this paper, a gate-level netlist-oriented FPGA-based timing analysis framework is proposed, offering a runtime-configuration mechanism for emulating different timing corner cases in hardware without requiring multiple FPGA bitstreams. Logic gates are instrumented with a quantization-based delay model and a critical path selection algorithm is used to reduce the FPGA resource overhead. For an exemplary design space exploration of stochastic CORDIC units, speed-up factors of up to 48 for 10 ps or 476 for 100 ps timing quantization are achieved while maintaining timing behavior deviations lower than 1.5% or 4% to timing simulations, respectively.
KW - CORDIC
KW - FPGA
KW - Stochastic Computing
KW - Timing analysis
KW - Timing behavior emulation
UR - http://www.scopus.com/inward/record.url?eid=2-s2.0-85061959584&partnerID=MN8TOARS
U2 - 10.1016/j.vlsi.2019.01.002
DO - 10.1016/j.vlsi.2019.01.002
M3 - Article
AN - SCOPUS:85061959584
VL - 69
SP - 120
EP - 137
JO - INTEGRATION
JF - INTEGRATION
SN - 0167-9260
ER -