Details
| Original language | English |
|---|---|
| Title of host publication | 2017 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS) |
| Subtitle of host publication | Proceedings |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 1-8 |
| Number of pages | 8 |
| ISBN (electronic) | 978-1-5090-6462-5 |
| ISBN (print) | 978-1-5090-6463-2 |
| Publication status | Published - Sept 2017 |
| Event | 27th International Symposium on Power and Timing Modeling, Optimization and Simulation, PATMOS 2017 - Thessaloniki, Greece Duration: 25 Sept 2017 → 27 Sept 2017 |
Abstract
ASJC Scopus subject areas
- Mathematics(all)
- Modelling and Simulation
- Computer Science(all)
- Computer Networks and Communications
- Computer Science(all)
- Hardware and Architecture
- Energy(all)
- Energy Engineering and Power Technology
- Engineering(all)
- Electrical and Electronic Engineering
- Mathematics(all)
- Control and Optimization
Sustainable Development Goals
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2017 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS): Proceedings. Institute of Electrical and Electronics Engineers Inc., 2017. p. 1-8.
Research output: Chapter in book/report/conference proceeding › Conference contribution › Research › peer review
}
TY - GEN
T1 - FLINT+
T2 - 27th International Symposium on Power and Timing Modeling, Optimization and Simulation, PATMOS 2017
AU - Weißbrich, Moritz
AU - Payá-Vayá, Guillermo
AU - Gerlach, Lukas
AU - Blume, Holger
AU - Najafi, A.
AU - García-Ortiz, A.
N1 - Funding information: This work was partly funded by the German Research Council (DFG) under project number PA 2762/1-1.
PY - 2017/9
Y1 - 2017/9
N2 - ASICs for Stochastic Computing conditions are designed for higher energy-efficiency or performance by sacrificing computational accuracy due to intentional circuit timing violations. To optimize the stochastic gate-level circuit behavior of a specific design, iterative timing analysis campaigns have to be carried out for a variety of chip temperature- and supply voltage-dependent timing corner cases. However, the application of common event-driven logic simulators usually leads to excessive analysis runtimes, increasing design time for hardware developers. In this paper, a gate-level netlist-oriented FPGA-based timing analysis framework is proposed, offering a runtime-configuration mechanism for emulating different timing corner cases in hardware without requiring multiple FPGA bitstreams. For an exemplary timing analysis campaign of an existing chip design, speed-up factors of up to 267 are achieved while maintaining timing behavior deviations lower than 1.05% to timing simulations.
AB - ASICs for Stochastic Computing conditions are designed for higher energy-efficiency or performance by sacrificing computational accuracy due to intentional circuit timing violations. To optimize the stochastic gate-level circuit behavior of a specific design, iterative timing analysis campaigns have to be carried out for a variety of chip temperature- and supply voltage-dependent timing corner cases. However, the application of common event-driven logic simulators usually leads to excessive analysis runtimes, increasing design time for hardware developers. In this paper, a gate-level netlist-oriented FPGA-based timing analysis framework is proposed, offering a runtime-configuration mechanism for emulating different timing corner cases in hardware without requiring multiple FPGA bitstreams. For an exemplary timing analysis campaign of an existing chip design, speed-up factors of up to 267 are achieved while maintaining timing behavior deviations lower than 1.05% to timing simulations.
UR - http://www.scopus.com/inward/record.url?scp=85043467254&partnerID=8YFLogxK
U2 - 10.1109/PATMOS.2017.8106956
DO - 10.1109/PATMOS.2017.8106956
M3 - Conference contribution
AN - SCOPUS:85043467254
SN - 978-1-5090-6463-2
SP - 1
EP - 8
BT - 2017 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 25 September 2017 through 27 September 2017
ER -