FLINT:: Layout-Oriented FPGA-Based Methodology for Fault Tolerant ASIC Design

Rochus Nowosielski; Lukas Gerlach; Stephan Bieband; Guillermo Paya-Vaya; Holger Blume

doi:10.7873/DATE.2015.0278

Details

Original language	English
Title of host publication	Proceedings of the 2015 Design, Automation and Test in Europe Conference and Exhibition (DATE)
Publisher	IEEE Computer Society
Pages	297-300
Number of pages	4
ISBN (electronic)	9783981537048
Publication status	Published - 22 Apr 2015
Event	2015 Design, Automation and Test in Europe Conference and Exhibition (DATE) - Grenoble, France Duration: 9 Mar 2015 → 13 Mar 2015

ASJC Scopus subject areas

Engineering(all)
General Engineering

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FLINT: Layout-Oriented FPGA-Based Methodology for Fault Tolerant ASIC Design. / Nowosielski, Rochus; Gerlach, Lukas; Bieband, Stephan et al.
Proceedings of the 2015 Design, Automation and Test in Europe Conference and Exhibition (DATE). IEEE Computer Society, 2015. p. 297-300.

Research output: Chapter in book/report/conference proceeding › Conference contribution › Research › peer review

Nowosielski, R, Gerlach, L, Bieband, S, Paya-Vaya, G & Blume, H 2015, FLINT: Layout-Oriented FPGA-Based Methodology for Fault Tolerant ASIC Design. in Proceedings of the 2015 Design, Automation and Test in Europe Conference and Exhibition (DATE). IEEE Computer Society, pp. 297-300, 2015 Design, Automation and Test in Europe Conference and Exhibition (DATE), Grenoble, France, 9 Mar 2015. https://doi.org/10.7873/DATE.2015.0278

Nowosielski, R., Gerlach, L., Bieband, S., Paya-Vaya, G., & Blume, H. (2015). FLINT: Layout-Oriented FPGA-Based Methodology for Fault Tolerant ASIC Design. In Proceedings of the 2015 Design, Automation and Test in Europe Conference and Exhibition (DATE) (pp. 297-300). IEEE Computer Society. https://doi.org/10.7873/DATE.2015.0278

Nowosielski R, Gerlach L, Bieband S, Paya-Vaya G, Blume H. FLINT: Layout-Oriented FPGA-Based Methodology for Fault Tolerant ASIC Design. In Proceedings of the 2015 Design, Automation and Test in Europe Conference and Exhibition (DATE). IEEE Computer Society. 2015. p. 297-300 doi: 10.7873/DATE.2015.0278

Nowosielski, Rochus ; Gerlach, Lukas ; Bieband, Stephan et al. / FLINT: Layout-Oriented FPGA-Based Methodology for Fault Tolerant ASIC Design. Proceedings of the 2015 Design, Automation and Test in Europe Conference and Exhibition (DATE). IEEE Computer Society, 2015. pp. 297-300

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Research@Leibniz University

FLINT: Layout-Oriented FPGA-Based Methodology for Fault Tolerant ASIC Design

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