Details
| Original language | English |
|---|---|
| Title of host publication | Proceedings |
| Subtitle of host publication | IEEE International Symposium on Circuits and Systems |
| Pages | 1583-1586 |
| Number of pages | 4 |
| Publication status | Published - 1993 |
| Event | 1993 IEEE International Symposium on Circuits and Systems - Chicago, IL, USA Duration: 3 May 1993 → 6 May 1993 |
Publication series
| Name | Proceedings - IEEE International Symposium on Circuits and Systems |
|---|---|
| Volume | 3 |
| ISSN (Print) | 0271-4310 |
Abstract
A fault-tolerant DCT-architecture based on distributed arithmetic has been developed. Fault-tolerance is achieved through a combination of distributed and residue arithmetic units. The implementation area of the presented architecture is about twice the size of a standard, non-fault-tolerant realization. Simulations on gate-level have shown, that about 75% of the logic area are protected against single static or dynamic stuck-at faults.
ASJC Scopus subject areas
- Engineering(all)
- Electrical and Electronic Engineering
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Proceedings : IEEE International Symposium on Circuits and Systems. 1993. p. 1583-1586 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 3).
Research output: Chapter in book/report/conference proceeding › Conference contribution › Research › peer review
}
TY - GEN
T1 - Fault-tolerant DCT-architecture based on distributed arithmetic
AU - Gaedke, Klaus
AU - Franzen, Jens
AU - Pirsch, Peter
PY - 1993
Y1 - 1993
N2 - A fault-tolerant DCT-architecture based on distributed arithmetic has been developed. Fault-tolerance is achieved through a combination of distributed and residue arithmetic units. The implementation area of the presented architecture is about twice the size of a standard, non-fault-tolerant realization. Simulations on gate-level have shown, that about 75% of the logic area are protected against single static or dynamic stuck-at faults.
AB - A fault-tolerant DCT-architecture based on distributed arithmetic has been developed. Fault-tolerance is achieved through a combination of distributed and residue arithmetic units. The implementation area of the presented architecture is about twice the size of a standard, non-fault-tolerant realization. Simulations on gate-level have shown, that about 75% of the logic area are protected against single static or dynamic stuck-at faults.
UR - http://www.scopus.com/inward/record.url?scp=0027245243&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:0027245243
SN - 0780312813
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
SP - 1583
EP - 1586
BT - Proceedings
T2 - 1993 IEEE International Symposium on Circuits and Systems
Y2 - 3 May 1993 through 6 May 1993
ER -