Details
| Original language | English |
|---|---|
| Title of host publication | 11th European Dependable Computing Conference |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 245-255 |
| Number of pages | 11 |
| ISBN (electronic) | 9781467392891 |
| Publication status | Published - 7 Jan 2016 |
| Externally published | Yes |
| Event | 11th European Dependable Computing Conference, EDCC 2015 - Paris, France Duration: 7 Sept 2015 → 11 Sept 2015 |
Abstract
Due to voltage and structure shrinking, the influence of radiation on a circuit's operation increases, resulting in future hardware designs exhibiting much higher rates of soft errors. Software developers have to cope with these effects to ensure functional safety. However, software-based hardware fault tolerance is a holistic property that is tricky to achieve in practice, potentially impaired by every single design decision. We present FAIL∗, an open and versatile architecture-level fault-injection (FI) framework for the continuous assessment and quantification of fault tolerance in an iterative software development process. FAIL∗ supplies the developer with reusable and composable FI campaigns, advanced pre-and post-processing analyses to easily identify sensitive spots in the software, well-abstracted back-end implementations for several hardware and simulator platforms, and scalability of FI campaigns by providing massive parallelization. We describe FAIL∗, its application to the development process of safety-critical software, and the lessons learned from a real-world example.
Keywords
- Continuous Fault-Resilience Assessment, Error-Detection Measures, Fault Resilience, Fault-Injection Tool, Hardware Fault Injection, Post-Injection Analysis, Quantification, Sensitive Spot Analysis, Software-Implemented Hardware Fault Tolerance
ASJC Scopus subject areas
- Computer Science(all)
- Computer Networks and Communications
- Computer Science(all)
- Hardware and Architecture
- Engineering(all)
- Safety, Risk, Reliability and Quality
Cite this
- Standard
- Harvard
- Apa
- Vancouver
- BibTeX
- RIS
11th European Dependable Computing Conference. Institute of Electrical and Electronics Engineers Inc., 2016. p. 245-255 7371972.
Research output: Chapter in book/report/conference proceeding › Conference contribution › Research › peer review
}
TY - GEN
T1 - FAIL∗: An Open and Versatile Fault-Injection Framework for the Assessment of Software-Implemented Hardware Fault Tolerance
AU - Schirmeier, Horst
AU - Hoffmann, Martin
AU - Dietrich, Christian
AU - Lenz, Michael
AU - Lohmann, Daniel
AU - Spinczyk, Olaf
PY - 2016/1/7
Y1 - 2016/1/7
N2 - Due to voltage and structure shrinking, the influence of radiation on a circuit's operation increases, resulting in future hardware designs exhibiting much higher rates of soft errors. Software developers have to cope with these effects to ensure functional safety. However, software-based hardware fault tolerance is a holistic property that is tricky to achieve in practice, potentially impaired by every single design decision. We present FAIL∗, an open and versatile architecture-level fault-injection (FI) framework for the continuous assessment and quantification of fault tolerance in an iterative software development process. FAIL∗ supplies the developer with reusable and composable FI campaigns, advanced pre-and post-processing analyses to easily identify sensitive spots in the software, well-abstracted back-end implementations for several hardware and simulator platforms, and scalability of FI campaigns by providing massive parallelization. We describe FAIL∗, its application to the development process of safety-critical software, and the lessons learned from a real-world example.
AB - Due to voltage and structure shrinking, the influence of radiation on a circuit's operation increases, resulting in future hardware designs exhibiting much higher rates of soft errors. Software developers have to cope with these effects to ensure functional safety. However, software-based hardware fault tolerance is a holistic property that is tricky to achieve in practice, potentially impaired by every single design decision. We present FAIL∗, an open and versatile architecture-level fault-injection (FI) framework for the continuous assessment and quantification of fault tolerance in an iterative software development process. FAIL∗ supplies the developer with reusable and composable FI campaigns, advanced pre-and post-processing analyses to easily identify sensitive spots in the software, well-abstracted back-end implementations for several hardware and simulator platforms, and scalability of FI campaigns by providing massive parallelization. We describe FAIL∗, its application to the development process of safety-critical software, and the lessons learned from a real-world example.
KW - Continuous Fault-Resilience Assessment
KW - Error-Detection Measures
KW - Fault Resilience
KW - Fault-Injection Tool
KW - Hardware Fault Injection
KW - Post-Injection Analysis
KW - Quantification
KW - Sensitive Spot Analysis
KW - Software-Implemented Hardware Fault Tolerance
UR - http://www.scopus.com/inward/record.url?scp=84966393568&partnerID=8YFLogxK
U2 - 10.1109/edcc.2015.28
DO - 10.1109/edcc.2015.28
M3 - Conference contribution
AN - SCOPUS:84966393568
SP - 245
EP - 255
BT - 11th European Dependable Computing Conference
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 11th European Dependable Computing Conference, EDCC 2015
Y2 - 7 September 2015 through 11 September 2015
ER -