Details
| Original language | English |
|---|---|
| Pages (from-to) | 541-569 |
| Number of pages | 29 |
| Journal | International Journal of Parallel Programming |
| Volume | 49 |
| Issue number | 4 |
| Early online date | 26 Dec 2020 |
| Publication status | Published - Aug 2021 |
Abstract
Microcontrollers to be used in harsh environmental conditions, e.g., at high temperatures or radiation exposition, need to be fabricated in robust technology nodes in order to operate reliably. However, these nodes are considerably larger than cutting-edge semiconductor technologies and provide less speed, drastically reducing system performance. In order to achieve low silicon area costs, low power consumption and reasonable performance, the processor architecture organization itself is a major influential design point. Parameters like data path width, instruction execution paradigm, code density, memory requirements, advanced control flow mechanisms etc., may have large effects on the design constraints. Application characteristics, like exploitable data parallelism and required arithmetic operations, have to be considered in order to use the implemented processor resources efficiently. In this paper, a design space exploration of five different architectures with MIPS- or ARM-compatible instruction set architectures, as well as transport-triggered instruction execution is presented. Using a 0.18 μ m SOI CMOS technology for high temperature and an exemplary case study from the fields of communication, i.e., powerline communication encoder, the influence of architectural parameters on performance and hardware efficiency is compared. For this application, a transport-triggered architecture configuration has an 8.5× higher performance and 2.4× higher computational energy efficiency at a 1.6× larger total silicon area than an off-the-shelf ARM Cortex-M0 embedded processor, showing the considerable range of design trade-offs for different architectures.
Keywords
- ASIC, Design tradeoff analysis, Harsh environment, Processor architecture organization, Transport-triggered architecture
ASJC Scopus subject areas
- Computer Science(all)
- Software
- Mathematics(all)
- Theoretical Computer Science
- Computer Science(all)
- Information Systems
Sustainable Development Goals
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In: International Journal of Parallel Programming, Vol. 49, No. 4, 08.2021, p. 541-569.
Research output: Contribution to journal › Article › Research › peer review
}
TY - JOUR
T1 - Evaluation of Different Processor Architecture Organizations for On-Site Electronics in Harsh Environments
AU - Gesper, Sven
AU - Weissbrich, Moritz
AU - Stuckenberg, Tobias
AU - Jaaskelainen, Pekka
AU - Blume, Holger
AU - Paya-Vaya, Guillermo
PY - 2021/8
Y1 - 2021/8
N2 - Microcontrollers to be used in harsh environmental conditions, e.g., at high temperatures or radiation exposition, need to be fabricated in robust technology nodes in order to operate reliably. However, these nodes are considerably larger than cutting-edge semiconductor technologies and provide less speed, drastically reducing system performance. In order to achieve low silicon area costs, low power consumption and reasonable performance, the processor architecture organization itself is a major influential design point. Parameters like data path width, instruction execution paradigm, code density, memory requirements, advanced control flow mechanisms etc., may have large effects on the design constraints. Application characteristics, like exploitable data parallelism and required arithmetic operations, have to be considered in order to use the implemented processor resources efficiently. In this paper, a design space exploration of five different architectures with MIPS- or ARM-compatible instruction set architectures, as well as transport-triggered instruction execution is presented. Using a 0.18 μ m SOI CMOS technology for high temperature and an exemplary case study from the fields of communication, i.e., powerline communication encoder, the influence of architectural parameters on performance and hardware efficiency is compared. For this application, a transport-triggered architecture configuration has an 8.5× higher performance and 2.4× higher computational energy efficiency at a 1.6× larger total silicon area than an off-the-shelf ARM Cortex-M0 embedded processor, showing the considerable range of design trade-offs for different architectures.
AB - Microcontrollers to be used in harsh environmental conditions, e.g., at high temperatures or radiation exposition, need to be fabricated in robust technology nodes in order to operate reliably. However, these nodes are considerably larger than cutting-edge semiconductor technologies and provide less speed, drastically reducing system performance. In order to achieve low silicon area costs, low power consumption and reasonable performance, the processor architecture organization itself is a major influential design point. Parameters like data path width, instruction execution paradigm, code density, memory requirements, advanced control flow mechanisms etc., may have large effects on the design constraints. Application characteristics, like exploitable data parallelism and required arithmetic operations, have to be considered in order to use the implemented processor resources efficiently. In this paper, a design space exploration of five different architectures with MIPS- or ARM-compatible instruction set architectures, as well as transport-triggered instruction execution is presented. Using a 0.18 μ m SOI CMOS technology for high temperature and an exemplary case study from the fields of communication, i.e., powerline communication encoder, the influence of architectural parameters on performance and hardware efficiency is compared. For this application, a transport-triggered architecture configuration has an 8.5× higher performance and 2.4× higher computational energy efficiency at a 1.6× larger total silicon area than an off-the-shelf ARM Cortex-M0 embedded processor, showing the considerable range of design trade-offs for different architectures.
KW - ASIC
KW - Design tradeoff analysis
KW - Harsh environment
KW - Processor architecture organization
KW - Transport-triggered architecture
UR - http://www.scopus.com/inward/record.url?scp=85098063494&partnerID=8YFLogxK
U2 - 10.1007/s10766-020-00686-8
DO - 10.1007/s10766-020-00686-8
M3 - Article
VL - 49
SP - 541
EP - 569
JO - International Journal of Parallel Programming
JF - International Journal of Parallel Programming
SN - 0885-7458
IS - 4
ER -