Efficient Emulation of Floating-Point Arithmetic on Fixed-Point SIMD Processors

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Original languageEnglish
Title of host publicationIEEE International Workshop on Signal Processing Systems
Subtitle of host publicationSiPS
PublisherIEEE Computer Society
Pages254-259
Number of pages6
ISBN (electronic)9781509033614
ISBN (print)978-1-5090-3362-1
Publication statusPublished - 12 Dec 2016
Event2016 IEEE International Workshop on Signal Processing Systems, SiPS 2016 - Dallas, United States
Duration: 26 Oct 201628 Oct 2016

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Efficient Emulation of Floating-Point Arithmetic on Fixed-Point SIMD Processors. / Gerlach, Lukas; Payá-Vayá, Guillermo; Blume, Holger.
IEEE International Workshop on Signal Processing Systems: SiPS. IEEE Computer Society, 2016. p. 254-259.

Research output: Chapter in book/report/conference proceedingConference contributionResearchpeer review

Gerlach, L, Payá-Vayá, G & Blume, H 2016, Efficient Emulation of Floating-Point Arithmetic on Fixed-Point SIMD Processors. in IEEE International Workshop on Signal Processing Systems: SiPS. IEEE Computer Society, pp. 254-259, 2016 IEEE International Workshop on Signal Processing Systems, SiPS 2016, Dallas, United States, 26 Oct 2016. https://doi.org/10.1109/SiPS.2016.52
Gerlach, L., Payá-Vayá, G., & Blume, H. (2016). Efficient Emulation of Floating-Point Arithmetic on Fixed-Point SIMD Processors. In IEEE International Workshop on Signal Processing Systems: SiPS (pp. 254-259). IEEE Computer Society. https://doi.org/10.1109/SiPS.2016.52
Gerlach L, Payá-Vayá G, Blume H. Efficient Emulation of Floating-Point Arithmetic on Fixed-Point SIMD Processors. In IEEE International Workshop on Signal Processing Systems: SiPS. IEEE Computer Society. 2016. p. 254-259 doi: 10.1109/SiPS.2016.52
Gerlach, Lukas ; Payá-Vayá, Guillermo ; Blume, Holger. / Efficient Emulation of Floating-Point Arithmetic on Fixed-Point SIMD Processors. IEEE International Workshop on Signal Processing Systems: SiPS. IEEE Computer Society, 2016. pp. 254-259
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