Details
| Original language | English |
|---|---|
| Title of host publication | 2009 IEEE Symposium on Industrial Electronics and Applications, ISIEA 2009 - Proceedings |
| Pages | 425-430 |
| Number of pages | 6 |
| Publication status | Published - 16 Dec 2009 |
| Event | 2009 IEEE Symposium on Industrial Electronics and Applications, ISIEA 2009 - Kuala Lumpur, Malaysia Duration: 4 Oct 2009 → 6 Oct 2009 |
Publication series
| Name | 2009 IEEE Symposium on Industrial Electronics and Applications, ISIEA 2009 - Proceedings |
|---|---|
| Volume | 1 |
Abstract
As IC technology scales down, the metal width is decreasing, making the resistance along the power lines increase substantially. Together with the nonlinear scaling of the threshold voltage that makes the ratio of the threshold voltage to the supply voltage rise, the IR drop becomes a serious problem in modern VLSI design. Thus, the verification of the power distribution network is of critical importance to ensure reliable performance. However, with the increasing number of transistors on a chip, the complexity of the power network has grown. The available computational power and memory resources impose limitations on the size of the networks that can be analyzed using currently known techniques. In this paper, we present a fast and efficient method to analyse power distribution networks in the time-domain. The key concepts in our approach are a current source-based model and a voltage controlled resistor. The library elements are pre-characterized with respect to the modeling requirements and their models are used during the transient simulation. The new contribution of this work is the use of a Selection Approach (SA) to reduce the number of current source models and to speed up the characterization time. The SA is a function of the input pattern, the energy consumed by the library cells and the placement of the cells in the layout. The proposed techniques provide good analysis results compared to the reference with a reduction of the run-time by a factor of 400, although the cell pre-characterization is based on SPICE simulation. Our model is independent of power network parasitics, which implies that different power network scenarios may be analyzed based on the same model and the same cell characterizations. The run-time and accuracy of the proposed approach are demonstrated on some industrial designs.
Keywords
- Cell library characteri- zation, Current source model, Selection approach, Voltage drop
ASJC Scopus subject areas
- Computer Science(all)
- Computer Networks and Communications
- Computer Science(all)
- Computer Science Applications
- Computer Science(all)
- Hardware and Architecture
- Engineering(all)
- Electrical and Electronic Engineering
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2009 IEEE Symposium on Industrial Electronics and Applications, ISIEA 2009 - Proceedings. 2009. p. 425-430 5356442 (2009 IEEE Symposium on Industrial Electronics and Applications, ISIEA 2009 - Proceedings; Vol. 1).
Research output: Chapter in book/report/conference proceeding › Conference contribution › Research › peer review
}
TY - GEN
T1 - Efficient and fast analysis of power distribution networks
AU - Harizi, Hedi
AU - Fischer, Horst
AU - Olbrich, Markus
AU - Barke, Erich
N1 - Copyright: Copyright 2010 Elsevier B.V., All rights reserved.
PY - 2009/12/16
Y1 - 2009/12/16
N2 - As IC technology scales down, the metal width is decreasing, making the resistance along the power lines increase substantially. Together with the nonlinear scaling of the threshold voltage that makes the ratio of the threshold voltage to the supply voltage rise, the IR drop becomes a serious problem in modern VLSI design. Thus, the verification of the power distribution network is of critical importance to ensure reliable performance. However, with the increasing number of transistors on a chip, the complexity of the power network has grown. The available computational power and memory resources impose limitations on the size of the networks that can be analyzed using currently known techniques. In this paper, we present a fast and efficient method to analyse power distribution networks in the time-domain. The key concepts in our approach are a current source-based model and a voltage controlled resistor. The library elements are pre-characterized with respect to the modeling requirements and their models are used during the transient simulation. The new contribution of this work is the use of a Selection Approach (SA) to reduce the number of current source models and to speed up the characterization time. The SA is a function of the input pattern, the energy consumed by the library cells and the placement of the cells in the layout. The proposed techniques provide good analysis results compared to the reference with a reduction of the run-time by a factor of 400, although the cell pre-characterization is based on SPICE simulation. Our model is independent of power network parasitics, which implies that different power network scenarios may be analyzed based on the same model and the same cell characterizations. The run-time and accuracy of the proposed approach are demonstrated on some industrial designs.
AB - As IC technology scales down, the metal width is decreasing, making the resistance along the power lines increase substantially. Together with the nonlinear scaling of the threshold voltage that makes the ratio of the threshold voltage to the supply voltage rise, the IR drop becomes a serious problem in modern VLSI design. Thus, the verification of the power distribution network is of critical importance to ensure reliable performance. However, with the increasing number of transistors on a chip, the complexity of the power network has grown. The available computational power and memory resources impose limitations on the size of the networks that can be analyzed using currently known techniques. In this paper, we present a fast and efficient method to analyse power distribution networks in the time-domain. The key concepts in our approach are a current source-based model and a voltage controlled resistor. The library elements are pre-characterized with respect to the modeling requirements and their models are used during the transient simulation. The new contribution of this work is the use of a Selection Approach (SA) to reduce the number of current source models and to speed up the characterization time. The SA is a function of the input pattern, the energy consumed by the library cells and the placement of the cells in the layout. The proposed techniques provide good analysis results compared to the reference with a reduction of the run-time by a factor of 400, although the cell pre-characterization is based on SPICE simulation. Our model is independent of power network parasitics, which implies that different power network scenarios may be analyzed based on the same model and the same cell characterizations. The run-time and accuracy of the proposed approach are demonstrated on some industrial designs.
KW - Cell library characteri- zation
KW - Current source model
KW - Selection approach
KW - Voltage drop
UR - http://www.scopus.com/inward/record.url?scp=76449091134&partnerID=8YFLogxK
U2 - 10.1109/ISIEA.2009.5356442
DO - 10.1109/ISIEA.2009.5356442
M3 - Conference contribution
AN - SCOPUS:76449091134
SN - 9781424446827
T3 - 2009 IEEE Symposium on Industrial Electronics and Applications, ISIEA 2009 - Proceedings
SP - 425
EP - 430
BT - 2009 IEEE Symposium on Industrial Electronics and Applications, ISIEA 2009 - Proceedings
T2 - 2009 IEEE Symposium on Industrial Electronics and Applications, ISIEA 2009
Y2 - 4 October 2009 through 6 October 2009
ER -