Details
| Original language | English |
|---|---|
| Title of host publication | Proceedings - 2007 International Conference on Embedded Computer Systems |
| Subtitle of host publication | Architectures, Modeling and Simulation, IC-SAMOS 2007 |
| Pages | 41-49 |
| Number of pages | 9 |
| Publication status | Published - 2007 |
| Event | 2007 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, IC-SAMOS 2007 - Samos, Greece Duration: 16 Jul 2007 → 19 Jul 2007 |
Abstract
This paper describes an enhanced list scheduling algorithm used on a parameterized assembler. The assembler, which is configurable in terms of architectural parameters, is used on a new environment system for exploring and optimizing VLIW architectures for multimedia applications. A generic VLIW architecture with a novel register file structure is used as a base architecture. The proposed scheduling algorithm includes sophisticated features. A backtracking technique allows to undo inappropriate scheduling decisions, while an advanced resource conflict function allows to work with different VLIW architecture configurations. Moreover, local register allocation in conjunction with the instruction scheduling process is also implemented for obtaining better code compaction. Two different multimedia tasks are implemented to check the correctness of the generated code for different architecture configurations. The code compaction efficiency, when scheduling these applications for different VLIW architecture configurations with a partitioned register file and limited number of functional units, reaches up to 94% of the compaction efficiency for the same configuration with an unconstrained register file and unlimited number of functional units.
ASJC Scopus subject areas
- Computer Science(all)
- General Computer Science
- Computer Science(all)
- Hardware and Architecture
- Engineering(all)
- Control and Systems Engineering
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Proceedings - 2007 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, IC-SAMOS 2007. 2007. p. 41-49 4285732.
Research output: Chapter in book/report/conference proceeding › Conference contribution › Research › peer review
}
TY - GEN
T1 - Design space exploration of media processors
T2 - 2007 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, IC-SAMOS 2007
AU - Payá-Vayá, Guillermo
AU - Martín-Langerwerf, Javier
AU - Taptimthong, Piriya
AU - Pirsch, Peter
PY - 2007
Y1 - 2007
N2 - This paper describes an enhanced list scheduling algorithm used on a parameterized assembler. The assembler, which is configurable in terms of architectural parameters, is used on a new environment system for exploring and optimizing VLIW architectures for multimedia applications. A generic VLIW architecture with a novel register file structure is used as a base architecture. The proposed scheduling algorithm includes sophisticated features. A backtracking technique allows to undo inappropriate scheduling decisions, while an advanced resource conflict function allows to work with different VLIW architecture configurations. Moreover, local register allocation in conjunction with the instruction scheduling process is also implemented for obtaining better code compaction. Two different multimedia tasks are implemented to check the correctness of the generated code for different architecture configurations. The code compaction efficiency, when scheduling these applications for different VLIW architecture configurations with a partitioned register file and limited number of functional units, reaches up to 94% of the compaction efficiency for the same configuration with an unconstrained register file and unlimited number of functional units.
AB - This paper describes an enhanced list scheduling algorithm used on a parameterized assembler. The assembler, which is configurable in terms of architectural parameters, is used on a new environment system for exploring and optimizing VLIW architectures for multimedia applications. A generic VLIW architecture with a novel register file structure is used as a base architecture. The proposed scheduling algorithm includes sophisticated features. A backtracking technique allows to undo inappropriate scheduling decisions, while an advanced resource conflict function allows to work with different VLIW architecture configurations. Moreover, local register allocation in conjunction with the instruction scheduling process is also implemented for obtaining better code compaction. Two different multimedia tasks are implemented to check the correctness of the generated code for different architecture configurations. The code compaction efficiency, when scheduling these applications for different VLIW architecture configurations with a partitioned register file and limited number of functional units, reaches up to 94% of the compaction efficiency for the same configuration with an unconstrained register file and unlimited number of functional units.
UR - http://www.scopus.com/inward/record.url?scp=47749086307&partnerID=8YFLogxK
U2 - 10.1109/ICSAMOS.2007.4285732
DO - 10.1109/ICSAMOS.2007.4285732
M3 - Conference contribution
AN - SCOPUS:47749086307
SN - 1424410584
SN - 9781424410583
SP - 41
EP - 49
BT - Proceedings - 2007 International Conference on Embedded Computer Systems
Y2 - 16 July 2007 through 19 July 2007
ER -