Details
| Original language | English |
|---|---|
| Title of host publication | 2008 Design, Automation and Test in Europe |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 56-61 |
| Number of pages | 6 |
| ISBN (print) | 978-3-9810801-3-1 |
| Publication status | Published - 11 Apr 2008 |
| Externally published | Yes |
| Event | Design, Automation and Test in Europe, DATE 2008 - Munich, Germany Duration: 10 Mar 2008 → 14 Mar 2008 |
Publication series
| Name | Proceedings -Design, Automation and Test in Europe, DATE |
|---|---|
| ISSN (Print) | 1530-1591 |
Abstract
Modern digital signal processing applications have an increasing demand for computational power while needing to preserve low power dissipation and high flexibility. For many applications, the growth of algorithmic complexity is already faster than the growth of computational power provided by discrete general purpose processors [1]. A typical approach to address this problem is the combination of a processor core with dedicated accelerators. Since changes in standards or algorithms can change the demands on the accelerators, an attractive alternative to highly customised VLSI-macros is the use of reconfigurable embedded FPGAs (eFPGAs). First commercial products combining a general purpose processor core and an embedded FPGA recently emerged (e.g. Stretch S6000 [2], Menta eFPGA-augmented CPUs [3]). For many digital signal processing applications, a significantly improved efficiency in terms of power dissipation, throughput and chip area can be achieved by tailoring both the processor core and the reconfigurable accelerator to the given application domain [4]. In this work, a methodology to design highly customisable eFPGA-architectures starting from a high level description is presented. The design framework elaborated during this work enables a physically optimised VLSI-design of the specified eFPGA and aims to support simulation of the according eFPGA-macros both on a functional and netlist-level by providing an elementary configuration tool based on the same high level description as the eFPGA-architecture.
ASJC Scopus subject areas
- Engineering(all)
- General Engineering
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2008 Design, Automation and Test in Europe. Institute of Electrical and Electronics Engineers Inc., 2008. p. 56-61 (Proceedings -Design, Automation and Test in Europe, DATE).
Research output: Chapter in book/report/conference proceeding › Conference contribution › Research › peer review
}
TY - GEN
T1 - Design flow for embedded FPGAs based on a flexible architecture template
AU - Neumann, B.
AU - Von Sydow, T.
AU - Blume, H.
AU - Noll, T. G.
PY - 2008/4/11
Y1 - 2008/4/11
N2 - Modern digital signal processing applications have an increasing demand for computational power while needing to preserve low power dissipation and high flexibility. For many applications, the growth of algorithmic complexity is already faster than the growth of computational power provided by discrete general purpose processors [1]. A typical approach to address this problem is the combination of a processor core with dedicated accelerators. Since changes in standards or algorithms can change the demands on the accelerators, an attractive alternative to highly customised VLSI-macros is the use of reconfigurable embedded FPGAs (eFPGAs). First commercial products combining a general purpose processor core and an embedded FPGA recently emerged (e.g. Stretch S6000 [2], Menta eFPGA-augmented CPUs [3]). For many digital signal processing applications, a significantly improved efficiency in terms of power dissipation, throughput and chip area can be achieved by tailoring both the processor core and the reconfigurable accelerator to the given application domain [4]. In this work, a methodology to design highly customisable eFPGA-architectures starting from a high level description is presented. The design framework elaborated during this work enables a physically optimised VLSI-design of the specified eFPGA and aims to support simulation of the according eFPGA-macros both on a functional and netlist-level by providing an elementary configuration tool based on the same high level description as the eFPGA-architecture.
AB - Modern digital signal processing applications have an increasing demand for computational power while needing to preserve low power dissipation and high flexibility. For many applications, the growth of algorithmic complexity is already faster than the growth of computational power provided by discrete general purpose processors [1]. A typical approach to address this problem is the combination of a processor core with dedicated accelerators. Since changes in standards or algorithms can change the demands on the accelerators, an attractive alternative to highly customised VLSI-macros is the use of reconfigurable embedded FPGAs (eFPGAs). First commercial products combining a general purpose processor core and an embedded FPGA recently emerged (e.g. Stretch S6000 [2], Menta eFPGA-augmented CPUs [3]). For many digital signal processing applications, a significantly improved efficiency in terms of power dissipation, throughput and chip area can be achieved by tailoring both the processor core and the reconfigurable accelerator to the given application domain [4]. In this work, a methodology to design highly customisable eFPGA-architectures starting from a high level description is presented. The design framework elaborated during this work enables a physically optimised VLSI-design of the specified eFPGA and aims to support simulation of the according eFPGA-macros both on a functional and netlist-level by providing an elementary configuration tool based on the same high level description as the eFPGA-architecture.
UR - http://www.scopus.com/inward/record.url?scp=49749134677&partnerID=8YFLogxK
U2 - 10.1109/DATE.2008.4484660
DO - 10.1109/DATE.2008.4484660
M3 - Conference contribution
AN - SCOPUS:49749134677
SN - 978-3-9810801-3-1
T3 - Proceedings -Design, Automation and Test in Europe, DATE
SP - 56
EP - 61
BT - 2008 Design, Automation and Test in Europe
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - Design, Automation and Test in Europe, DATE 2008
Y2 - 10 March 2008 through 14 March 2008
ER -