Details
| Original language | English |
|---|---|
| Pages (from-to) | 1724-1728 |
| Number of pages | 5 |
| Journal | Microelectronics reliability |
| Volume | 54 |
| Issue number | 9-10 |
| Publication status | Published - 1 Sept 2014 |
Abstract
The miniaturization process of CMOS components creates new challenges for the development of integrated circuits. Especially the connections with a tungsten via between two metal layers can be a problem. Changes in geometry can bear on reliability problems. For a robust metallization design it is necessary to know, how strong the influence of the tungsten via alignment affects the physical behavior. The lifetime of up- and downstream test structures with different overlaps as well as strong misalignment was determined by measurements. Investigations have shown that the alignments have a noticeable effect on the reliability and performance of test structures. The downstream line shows the expected lifetime behavior. For the upstream line no influence of the misalignment on the lifetime was found. Simulations are taken into account to understand the thermal-electrical and mechanical behavior.
Keywords
- Electromigration, Metallization, Reliability, Simulation
ASJC Scopus subject areas
- Materials Science(all)
- Electronic, Optical and Magnetic Materials
- Physics and Astronomy(all)
- Atomic and Molecular Physics, and Optics
- Engineering(all)
- Safety, Risk, Reliability and Quality
- Physics and Astronomy(all)
- Condensed Matter Physics
- Materials Science(all)
- Surfaces, Coatings and Films
- Engineering(all)
- Electrical and Electronic Engineering
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In: Microelectronics reliability, Vol. 54, No. 9-10, 01.09.2014, p. 1724-1728.
Research output: Contribution to journal › Article › Research › peer review
}
TY - JOUR
T1 - Degradation behavior in upstream/downstream via test structures
AU - Kludt, J.
AU - Weide-Zaage, K.
AU - Ackermann, M.
AU - Hein, V.
AU - Kovács, C.
N1 - Publisher Copyright: © 2014 Elsevier Ltd. All rights reserved. Copyright: Copyright 2014 Elsevier B.V., All rights reserved.
PY - 2014/9/1
Y1 - 2014/9/1
N2 - The miniaturization process of CMOS components creates new challenges for the development of integrated circuits. Especially the connections with a tungsten via between two metal layers can be a problem. Changes in geometry can bear on reliability problems. For a robust metallization design it is necessary to know, how strong the influence of the tungsten via alignment affects the physical behavior. The lifetime of up- and downstream test structures with different overlaps as well as strong misalignment was determined by measurements. Investigations have shown that the alignments have a noticeable effect on the reliability and performance of test structures. The downstream line shows the expected lifetime behavior. For the upstream line no influence of the misalignment on the lifetime was found. Simulations are taken into account to understand the thermal-electrical and mechanical behavior.
AB - The miniaturization process of CMOS components creates new challenges for the development of integrated circuits. Especially the connections with a tungsten via between two metal layers can be a problem. Changes in geometry can bear on reliability problems. For a robust metallization design it is necessary to know, how strong the influence of the tungsten via alignment affects the physical behavior. The lifetime of up- and downstream test structures with different overlaps as well as strong misalignment was determined by measurements. Investigations have shown that the alignments have a noticeable effect on the reliability and performance of test structures. The downstream line shows the expected lifetime behavior. For the upstream line no influence of the misalignment on the lifetime was found. Simulations are taken into account to understand the thermal-electrical and mechanical behavior.
KW - Electromigration
KW - Metallization
KW - Reliability
KW - Simulation
UR - http://www.scopus.com/inward/record.url?scp=84908501099&partnerID=8YFLogxK
U2 - 10.1016/j.microrel.2014.07.042
DO - 10.1016/j.microrel.2014.07.042
M3 - Article
AN - SCOPUS:84908501099
VL - 54
SP - 1724
EP - 1728
JO - Microelectronics reliability
JF - Microelectronics reliability
SN - 0026-2714
IS - 9-10
ER -