Details
| Original language | English |
|---|---|
| Pages (from-to) | 271-282 |
| Number of pages | 12 |
| Journal | Proceedings of the International Conference on Application Specific Array Processors |
| Publication status | Published - 1994 |
| Event | 1994 International Conference on Application Specific Array Processors - San Francisco, CA, USA Duration: 22 Aug 1994 → 24 Aug 1994 |
Abstract
A data path array design combining shared memory communication among the data paths and address and control autonomy of the array elements leads to the powerful core of a high-performance digital signal processor (DSP) on a wide field of image processing applications. Assuming 100 MHz clock frequency for a 4 × 4 array, the processor will perform a 1024 samples complex FFT within 3 μs including data I/O. The Hough transform of a 512 × 512 pel image with 30% black pels is performed within 66 ms, assuming 7 bit quantization for the angle and 11 bit quantization for the radius, thus achieving a sustained arithmetic performance of 2.8 Giga operations per second (GOPS).
ASJC Scopus subject areas
- Computer Science(all)
- Hardware and Architecture
- Computer Science(all)
- Computer Networks and Communications
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In: Proceedings of the International Conference on Application Specific Array Processors, 1994, p. 271-282.
Research output: Contribution to journal › Conference article › Research › peer review
}
TY - JOUR
T1 - Data path array with shared memory as core of a high performance DSP
AU - Kneip, J.
AU - Roenner, K.
AU - Pirsch, P.
PY - 1994
Y1 - 1994
N2 - A data path array design combining shared memory communication among the data paths and address and control autonomy of the array elements leads to the powerful core of a high-performance digital signal processor (DSP) on a wide field of image processing applications. Assuming 100 MHz clock frequency for a 4 × 4 array, the processor will perform a 1024 samples complex FFT within 3 μs including data I/O. The Hough transform of a 512 × 512 pel image with 30% black pels is performed within 66 ms, assuming 7 bit quantization for the angle and 11 bit quantization for the radius, thus achieving a sustained arithmetic performance of 2.8 Giga operations per second (GOPS).
AB - A data path array design combining shared memory communication among the data paths and address and control autonomy of the array elements leads to the powerful core of a high-performance digital signal processor (DSP) on a wide field of image processing applications. Assuming 100 MHz clock frequency for a 4 × 4 array, the processor will perform a 1024 samples complex FFT within 3 μs including data I/O. The Hough transform of a 512 × 512 pel image with 30% black pels is performed within 66 ms, assuming 7 bit quantization for the angle and 11 bit quantization for the radius, thus achieving a sustained arithmetic performance of 2.8 Giga operations per second (GOPS).
UR - http://www.scopus.com/inward/record.url?scp=0028573154&partnerID=8YFLogxK
M3 - Conference article
AN - SCOPUS:0028573154
SP - 271
EP - 282
JO - Proceedings of the International Conference on Application Specific Array Processors
JF - Proceedings of the International Conference on Application Specific Array Processors
SN - 1063-6862
T2 - 1994 International Conference on Application Specific Array Processors
Y2 - 22 August 1994 through 24 August 1994
ER -