Details
Original language | English |
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Title of host publication | Proceedings of the 55th Annual Design Automation Conference, DAC 2018 |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
ISBN (print) | 9781450357005 |
Publication status | Published - Jun 2018 |
Event | 55th Annual Design Automation Conference, DAC 2018 - San Francisco, United States Duration: 24 Jun 2018 → 29 Jun 2018 |
Publication series
Name | Proceedings - Design Automation Conference |
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Volume | Part F137710 |
ISSN (Print) | 0738-100X |
Abstract
With shrinking structure sizes, soft-error mitigation has become a major challenge in the design and certification of safety-critical embedded systems. Their robustness is quantified by extensive faultinjection campaigns, which on hardware level can nevertheless cover only a tiny part of the fault space. We suggest Fault-Masking Terms (MATEs) to effectively prune the fault space for gate-level fault injection campaigns by using the (software-induced) hardware state to dynamically cut off benign faults. Our tool applied to an AVR core and a size-optimized MSP430 implementation shows that up to 21 percent of all SEUs on flip-flop level are masked within one clock cycle.
ASJC Scopus subject areas
- Computer Science(all)
- Computer Science Applications
- Engineering(all)
- Control and Systems Engineering
- Engineering(all)
- Electrical and Electronic Engineering
- Mathematics(all)
- Modelling and Simulation
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Proceedings of the 55th Annual Design Automation Conference, DAC 2018. Institute of Electrical and Electronics Engineers Inc., 2018. 79 (Proceedings - Design Automation Conference; Vol. Part F137710).
Research output: Chapter in book/report/conference proceeding › Conference contribution › Research › peer review
}
TY - GEN
T1 - Cross-Layer Fault-Space Pruning for Hardware-Assisted Fault Injection
AU - Dietrich, Christian
AU - Schmider, Achim
AU - Pusz, Oskar
AU - Payá Vayá, Guillermo
AU - Lohmann, Daniel
N1 - Funding information: The authors thank the anonymous reviewers and Horst Schirmeier for their feedback. This work has been supported by the German Research Foundation (DFG) under the grants no. LO 1719/4-1.
PY - 2018/6
Y1 - 2018/6
N2 - With shrinking structure sizes, soft-error mitigation has become a major challenge in the design and certification of safety-critical embedded systems. Their robustness is quantified by extensive faultinjection campaigns, which on hardware level can nevertheless cover only a tiny part of the fault space. We suggest Fault-Masking Terms (MATEs) to effectively prune the fault space for gate-level fault injection campaigns by using the (software-induced) hardware state to dynamically cut off benign faults. Our tool applied to an AVR core and a size-optimized MSP430 implementation shows that up to 21 percent of all SEUs on flip-flop level are masked within one clock cycle.
AB - With shrinking structure sizes, soft-error mitigation has become a major challenge in the design and certification of safety-critical embedded systems. Their robustness is quantified by extensive faultinjection campaigns, which on hardware level can nevertheless cover only a tiny part of the fault space. We suggest Fault-Masking Terms (MATEs) to effectively prune the fault space for gate-level fault injection campaigns by using the (software-induced) hardware state to dynamically cut off benign faults. Our tool applied to an AVR core and a size-optimized MSP430 implementation shows that up to 21 percent of all SEUs on flip-flop level are masked within one clock cycle.
UR - http://www.scopus.com/inward/record.url?scp=85053685946&partnerID=8YFLogxK
U2 - 10.1145/3195970.3196019
DO - 10.1145/3195970.3196019
M3 - Conference contribution
AN - SCOPUS:85053685946
SN - 9781450357005
T3 - Proceedings - Design Automation Conference
BT - Proceedings of the 55th Annual Design Automation Conference, DAC 2018
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 55th Annual Design Automation Conference, DAC 2018
Y2 - 24 June 2018 through 29 June 2018
ER -