Core interconnect testing hazards

Research output: Contribution to journalConference articleResearchpeer review

Authors

  • Petra Nordholz
  • Hartmut Grabinski
  • Dieter Treytnar
  • Jan Otterstedt
  • Dirk Niggemeyer
  • Uwe Arz
  • T. W. Williams

External Research Organisations

  • IBM
View graph of relations

Details

Original languageEnglish
Article number655985
Pages (from-to)953-954
Number of pages2
JournalProceedings -Design, Automation and Test in Europe, DATE
Publication statusPublished - 1998
EventDesign, Automation and Test in Europe, DATE 1998 - Paris, France
Duration: 23 Feb 199826 Feb 1998

Abstract

Interconnects must not only be analyzed with regard to opens and shorts but also with regard to the signal delays. Up to now, opens and shorts in bus systems on boards have been tested using boundary scan, mostly neglecting delay test. In addition, it has to be considered that the signal delay (i.e. the time when the signal crosses the switching threshold of the following gate) on a certain line within a bus system depends on the set of input signals of all bus lines. Furthermore, hazards can occur due to coupling between bus lines which can lead to an incorrect function of the whole circuit. Different interconnect systems with different test patterns have been analyzed and the results for 0.10 μm technology will be given. The geometric data for the interconnects in 0.10 μm technology has been derived or directly extracted from the SIA-Roadmap. With this data the line parameters for the simulation of the interconnects have been calculated with the help of a tool which takes into account conducting substrates.

ASJC Scopus subject areas

Cite this

Core interconnect testing hazards. / Nordholz, Petra; Grabinski, Hartmut; Treytnar, Dieter et al.
In: Proceedings -Design, Automation and Test in Europe, DATE, 1998, p. 953-954.

Research output: Contribution to journalConference articleResearchpeer review

Nordholz, P, Grabinski, H, Treytnar, D, Otterstedt, J, Niggemeyer, D, Arz, U & Williams, TW 1998, 'Core interconnect testing hazards', Proceedings -Design, Automation and Test in Europe, DATE, pp. 953-954. https://doi.org/10.1109/DATE.1998.655985
Nordholz, P., Grabinski, H., Treytnar, D., Otterstedt, J., Niggemeyer, D., Arz, U., & Williams, T. W. (1998). Core interconnect testing hazards. Proceedings -Design, Automation and Test in Europe, DATE, 953-954. Article 655985. https://doi.org/10.1109/DATE.1998.655985
Nordholz P, Grabinski H, Treytnar D, Otterstedt J, Niggemeyer D, Arz U et al. Core interconnect testing hazards. Proceedings -Design, Automation and Test in Europe, DATE. 1998;953-954. 655985. doi: 10.1109/DATE.1998.655985
Nordholz, Petra ; Grabinski, Hartmut ; Treytnar, Dieter et al. / Core interconnect testing hazards. In: Proceedings -Design, Automation and Test in Europe, DATE. 1998 ; pp. 953-954.
Download
@article{b236e6e3012849fbaa232a048a7fcd21,
title = "Core interconnect testing hazards",
abstract = "Interconnects must not only be analyzed with regard to opens and shorts but also with regard to the signal delays. Up to now, opens and shorts in bus systems on boards have been tested using boundary scan, mostly neglecting delay test. In addition, it has to be considered that the signal delay (i.e. the time when the signal crosses the switching threshold of the following gate) on a certain line within a bus system depends on the set of input signals of all bus lines. Furthermore, hazards can occur due to coupling between bus lines which can lead to an incorrect function of the whole circuit. Different interconnect systems with different test patterns have been analyzed and the results for 0.10 μm technology will be given. The geometric data for the interconnects in 0.10 μm technology has been derived or directly extracted from the SIA-Roadmap. With this data the line parameters for the simulation of the interconnects have been calculated with the help of a tool which takes into account conducting substrates.",
author = "Petra Nordholz and Hartmut Grabinski and Dieter Treytnar and Jan Otterstedt and Dirk Niggemeyer and Uwe Arz and Williams, {T. W.}",
year = "1998",
doi = "10.1109/DATE.1998.655985",
language = "English",
pages = "953--954",
note = "Design, Automation and Test in Europe, DATE 1998 ; Conference date: 23-02-1998 Through 26-02-1998",

}

Download

TY - JOUR

T1 - Core interconnect testing hazards

AU - Nordholz, Petra

AU - Grabinski, Hartmut

AU - Treytnar, Dieter

AU - Otterstedt, Jan

AU - Niggemeyer, Dirk

AU - Arz, Uwe

AU - Williams, T. W.

PY - 1998

Y1 - 1998

N2 - Interconnects must not only be analyzed with regard to opens and shorts but also with regard to the signal delays. Up to now, opens and shorts in bus systems on boards have been tested using boundary scan, mostly neglecting delay test. In addition, it has to be considered that the signal delay (i.e. the time when the signal crosses the switching threshold of the following gate) on a certain line within a bus system depends on the set of input signals of all bus lines. Furthermore, hazards can occur due to coupling between bus lines which can lead to an incorrect function of the whole circuit. Different interconnect systems with different test patterns have been analyzed and the results for 0.10 μm technology will be given. The geometric data for the interconnects in 0.10 μm technology has been derived or directly extracted from the SIA-Roadmap. With this data the line parameters for the simulation of the interconnects have been calculated with the help of a tool which takes into account conducting substrates.

AB - Interconnects must not only be analyzed with regard to opens and shorts but also with regard to the signal delays. Up to now, opens and shorts in bus systems on boards have been tested using boundary scan, mostly neglecting delay test. In addition, it has to be considered that the signal delay (i.e. the time when the signal crosses the switching threshold of the following gate) on a certain line within a bus system depends on the set of input signals of all bus lines. Furthermore, hazards can occur due to coupling between bus lines which can lead to an incorrect function of the whole circuit. Different interconnect systems with different test patterns have been analyzed and the results for 0.10 μm technology will be given. The geometric data for the interconnects in 0.10 μm technology has been derived or directly extracted from the SIA-Roadmap. With this data the line parameters for the simulation of the interconnects have been calculated with the help of a tool which takes into account conducting substrates.

UR - http://www.scopus.com/inward/record.url?scp=84893727824&partnerID=8YFLogxK

U2 - 10.1109/DATE.1998.655985

DO - 10.1109/DATE.1998.655985

M3 - Conference article

AN - SCOPUS:84893727824

SP - 953

EP - 954

JO - Proceedings -Design, Automation and Test in Europe, DATE

JF - Proceedings -Design, Automation and Test in Europe, DATE

SN - 1530-1591

M1 - 655985

T2 - Design, Automation and Test in Europe, DATE 1998

Y2 - 23 February 1998 through 26 February 1998

ER -