Details
| Original language | English |
|---|---|
| Pages | 561-568 |
| Number of pages | 8 |
| Publication status | Published - 1998 |
| Event | 1998 IEEE Workshop on Signal Processing Systems, SIPS - Cambridge, MA, USA Duration: 8 Oct 1998 → 10 Oct 1998 |
Conference
| Conference | 1998 IEEE Workshop on Signal Processing Systems, SIPS |
|---|---|
| City | Cambridge, MA, USA |
| Period | 8 Oct 1998 → 10 Oct 1998 |
Abstract
Driven by the rapid advances in semiconductor technology the number of functional units that can be implemented on a single chip is rapidly increasing. This raises the need for programmable but small processor cores to handle control of operation as well as communication and synchronization between the different functional modules on the chip. We have developed a soft core generator for highly parameterizable RISC-cores. The instruction word width can be arbitrarily chosen between 8 and 32 bits. Independent of this, the data-path width can be selected between 8 and 64 bits respectively. DSP-like performance can be achieved with the instantiation of a 64-bit (splitable-) MAC-unit in the data-path. The number of registers is arbitrarily scalable. The resulting cores are generated in RTL-VHDL and are fully synthesizable. Worst-case timing simulation shows 100 MHz achievable clock-speed using a 3LM 0.5 μm standard-cell technology. The size of the synthesized cores ranges from 900 gates for a multi-cycle 8 bit core to 10 k gates for a 5-stage pipelined 32 bit core with 8 registers. Interfaces and behavioral models are provided for instruction and data memories as well as a runable VHDL testbench with basic test patterns. As a result, a 16 bit RISC core with instruction and data memories can be implemented on 1 mm2 of silicon area in a 0.35 μm technology.
ASJC Scopus subject areas
- Computer Science(all)
- Signal Processing
- Engineering(all)
- Media Technology
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1998. 561-568 Paper presented at 1998 IEEE Workshop on Signal Processing Systems, SIPS, Cambridge, MA, USA.
Research output: Contribution to conference › Paper › Research › peer review
}
TY - CONF
T1 - Core generator for fully synthesizable and highly parameterizable RISC-cores for system-on-chip designs
AU - Berekovic, Mladen
AU - Heistermann, Dirk
AU - Pirsch, Peter
PY - 1998
Y1 - 1998
N2 - Driven by the rapid advances in semiconductor technology the number of functional units that can be implemented on a single chip is rapidly increasing. This raises the need for programmable but small processor cores to handle control of operation as well as communication and synchronization between the different functional modules on the chip. We have developed a soft core generator for highly parameterizable RISC-cores. The instruction word width can be arbitrarily chosen between 8 and 32 bits. Independent of this, the data-path width can be selected between 8 and 64 bits respectively. DSP-like performance can be achieved with the instantiation of a 64-bit (splitable-) MAC-unit in the data-path. The number of registers is arbitrarily scalable. The resulting cores are generated in RTL-VHDL and are fully synthesizable. Worst-case timing simulation shows 100 MHz achievable clock-speed using a 3LM 0.5 μm standard-cell technology. The size of the synthesized cores ranges from 900 gates for a multi-cycle 8 bit core to 10 k gates for a 5-stage pipelined 32 bit core with 8 registers. Interfaces and behavioral models are provided for instruction and data memories as well as a runable VHDL testbench with basic test patterns. As a result, a 16 bit RISC core with instruction and data memories can be implemented on 1 mm2 of silicon area in a 0.35 μm technology.
AB - Driven by the rapid advances in semiconductor technology the number of functional units that can be implemented on a single chip is rapidly increasing. This raises the need for programmable but small processor cores to handle control of operation as well as communication and synchronization between the different functional modules on the chip. We have developed a soft core generator for highly parameterizable RISC-cores. The instruction word width can be arbitrarily chosen between 8 and 32 bits. Independent of this, the data-path width can be selected between 8 and 64 bits respectively. DSP-like performance can be achieved with the instantiation of a 64-bit (splitable-) MAC-unit in the data-path. The number of registers is arbitrarily scalable. The resulting cores are generated in RTL-VHDL and are fully synthesizable. Worst-case timing simulation shows 100 MHz achievable clock-speed using a 3LM 0.5 μm standard-cell technology. The size of the synthesized cores ranges from 900 gates for a multi-cycle 8 bit core to 10 k gates for a 5-stage pipelined 32 bit core with 8 registers. Interfaces and behavioral models are provided for instruction and data memories as well as a runable VHDL testbench with basic test patterns. As a result, a 16 bit RISC core with instruction and data memories can be implemented on 1 mm2 of silicon area in a 0.35 μm technology.
UR - http://www.scopus.com/inward/record.url?scp=0031624589&partnerID=8YFLogxK
M3 - Paper
AN - SCOPUS:0031624589
SP - 561
EP - 568
T2 - 1998 IEEE Workshop on Signal Processing Systems, SIPS
Y2 - 8 October 1998 through 10 October 1998
ER -