Details
| Original language | English |
|---|---|
| Pages (from-to) | II-180-II-183 |
| Journal | Proceedings - IEEE International Symposium on Circuits and Systems |
| Volume | 2 |
| Publication status | Published - 2000 |
Abstract
The TANGRAM VLSI co-processor is intended to assist existing MPEG-4 video-decoders to perform the computation intensive final step of MPEG-4 video decoding: compositing of scenes at the display. TANGRAM consists of a RISC control processor and multiple powerful arithmetic units that perform rendering calculations directly in hardware. This hybrid architecture enables adaptation to changes in algorithms or support for different video-formats in software. Communication to a host CPU and video decoding hardware is done via the very common Pl-bus on-chip interface. TANGRAM directly interfaces with the ITU-R601/656 digital video output. VHDL implementation and synthesis for a 0.35 μ standard-cell library provide an estimate of 100 MHz achievable clock-frequency (worst-case), 52 mm2 overall area and 1 Watt power dissipation. TANGRAM has sufficient performance for rendering of MPEG-4 Main ProfileLayer3 scenes (CCIR).
ASJC Scopus subject areas
- Engineering(all)
- Electrical and Electronic Engineering
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In: Proceedings - IEEE International Symposium on Circuits and Systems, Vol. 2, 2000, p. II-180-II-183.
Research output: Contribution to journal › Article › Research › peer review
}
TY - JOUR
T1 - Co-processor architecture for MPEG-4 main profile visual compositing
AU - Berekovic, M.
AU - Pirsch, P.
AU - Selinger, T.
AU - Wels, K. I.
AU - Miro, C.
AU - Lafage, A.
AU - Heer, C.
AU - Ghigo, G.
PY - 2000
Y1 - 2000
N2 - The TANGRAM VLSI co-processor is intended to assist existing MPEG-4 video-decoders to perform the computation intensive final step of MPEG-4 video decoding: compositing of scenes at the display. TANGRAM consists of a RISC control processor and multiple powerful arithmetic units that perform rendering calculations directly in hardware. This hybrid architecture enables adaptation to changes in algorithms or support for different video-formats in software. Communication to a host CPU and video decoding hardware is done via the very common Pl-bus on-chip interface. TANGRAM directly interfaces with the ITU-R601/656 digital video output. VHDL implementation and synthesis for a 0.35 μ standard-cell library provide an estimate of 100 MHz achievable clock-frequency (worst-case), 52 mm2 overall area and 1 Watt power dissipation. TANGRAM has sufficient performance for rendering of MPEG-4 Main ProfileLayer3 scenes (CCIR).
AB - The TANGRAM VLSI co-processor is intended to assist existing MPEG-4 video-decoders to perform the computation intensive final step of MPEG-4 video decoding: compositing of scenes at the display. TANGRAM consists of a RISC control processor and multiple powerful arithmetic units that perform rendering calculations directly in hardware. This hybrid architecture enables adaptation to changes in algorithms or support for different video-formats in software. Communication to a host CPU and video decoding hardware is done via the very common Pl-bus on-chip interface. TANGRAM directly interfaces with the ITU-R601/656 digital video output. VHDL implementation and synthesis for a 0.35 μ standard-cell library provide an estimate of 100 MHz achievable clock-frequency (worst-case), 52 mm2 overall area and 1 Watt power dissipation. TANGRAM has sufficient performance for rendering of MPEG-4 Main ProfileLayer3 scenes (CCIR).
UR - http://www.scopus.com/inward/record.url?scp=0033684007&partnerID=8YFLogxK
U2 - 10.1109/ISCAS.2000.856288
DO - 10.1109/ISCAS.2000.856288
M3 - Article
AN - SCOPUS:0033684007
VL - 2
SP - II-180-II-183
JO - Proceedings - IEEE International Symposium on Circuits and Systems
JF - Proceedings - IEEE International Symposium on Circuits and Systems
SN - 0271-4310
ER -