Details
| Original language | English |
|---|---|
| Article number | 9080548 |
| Pages (from-to) | 3035-3046 |
| Number of pages | 12 |
| Journal | IEEE Transactions on Circuits and Systems I: Regular Papers |
| Volume | 67 |
| Issue number | 9 |
| Publication status | Published - 9 Sept 2020 |
Abstract
In this paper, we analyze how to calculate the matrix transposition in continuous flow by using a memory or group of memories. The proposed approach studies this problem for specific conditions such as square and non-square matrices, use of limited access memories and use of several memories in parallel. Contrary to previous approaches, which are based on specific cases or examples, the proposed approach derives the fundamental theory involved in the problem of matrix transposition in a continuous flow. This allows for obtaining the exact equations for the read and write addresses of the memories and other control signals in the circuits. Furthermore, the cases that involve non-square matrices, which have not been studied in detail in the literature, are analyzed in depth in this paper. Experimental results show that the proposed approach is capable of transposing matrices of 8192 times 8192 32-bit data received in series at a rate of 200 mega samples per second, which doubles the throughput of previous approaches.
Keywords
- Continuous flow, external memory, matrix transposition, pipelined architecture, SDRAM
ASJC Scopus subject areas
- Engineering(all)
- Electrical and Electronic Engineering
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In: IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 67, No. 9, 9080548, 09.09.2020, p. 3035-3046.
Research output: Contribution to journal › Article › Research › peer review
}
TY - JOUR
T1 - Continuous-Flow Matrix Transposition Using Memories
AU - Garrido, Mario
AU - Pirsch, Peter
N1 - Funding Information: Manuscript received November 20, 2019; revised February 4, 2020 and March 14, 2020; accepted April 8, 2020. Date of publication April 28, 2020; date of current version September 2, 2020. This work was supported by the Ramón y Cajal Fellowship of the Spanish Ministry of Science, Innovation, and Universities, under Grant RYC2018-025384-I. This article was recommended by Associate Editor M. M. Kermani. (Corresponding author: Mario Garrido.) Mario Garrido is with the Department of Electronic Engineering, ETSI de Telecomunicación, Universidad Politécnica de Madrid, 28040 Madrid, Spain (e-mail: mario.garrido@upm.es).
PY - 2020/9/9
Y1 - 2020/9/9
N2 - In this paper, we analyze how to calculate the matrix transposition in continuous flow by using a memory or group of memories. The proposed approach studies this problem for specific conditions such as square and non-square matrices, use of limited access memories and use of several memories in parallel. Contrary to previous approaches, which are based on specific cases or examples, the proposed approach derives the fundamental theory involved in the problem of matrix transposition in a continuous flow. This allows for obtaining the exact equations for the read and write addresses of the memories and other control signals in the circuits. Furthermore, the cases that involve non-square matrices, which have not been studied in detail in the literature, are analyzed in depth in this paper. Experimental results show that the proposed approach is capable of transposing matrices of 8192 times 8192 32-bit data received in series at a rate of 200 mega samples per second, which doubles the throughput of previous approaches.
AB - In this paper, we analyze how to calculate the matrix transposition in continuous flow by using a memory or group of memories. The proposed approach studies this problem for specific conditions such as square and non-square matrices, use of limited access memories and use of several memories in parallel. Contrary to previous approaches, which are based on specific cases or examples, the proposed approach derives the fundamental theory involved in the problem of matrix transposition in a continuous flow. This allows for obtaining the exact equations for the read and write addresses of the memories and other control signals in the circuits. Furthermore, the cases that involve non-square matrices, which have not been studied in detail in the literature, are analyzed in depth in this paper. Experimental results show that the proposed approach is capable of transposing matrices of 8192 times 8192 32-bit data received in series at a rate of 200 mega samples per second, which doubles the throughput of previous approaches.
KW - Continuous flow
KW - external memory
KW - matrix transposition
KW - pipelined architecture
KW - SDRAM
UR - http://www.scopus.com/inward/record.url?scp=85090406847&partnerID=8YFLogxK
U2 - 10.1109/TCSI.2020.2987736
DO - 10.1109/TCSI.2020.2987736
M3 - Article
AN - SCOPUS:85090406847
VL - 67
SP - 3035
EP - 3046
JO - IEEE Transactions on Circuits and Systems I: Regular Papers
JF - IEEE Transactions on Circuits and Systems I: Regular Papers
SN - 1549-8328
IS - 9
M1 - 9080548
ER -