Details
| Original language | English |
|---|---|
| Article number | 101647 |
| Journal | Journal of Systems Architecture |
| Volume | 100 |
| Early online date | 3 Oct 2019 |
| Publication status | Published - 7 Nov 2019 |
Abstract
Embedded automotive Computer Vision systems for real-time motion tracking and 3D scene reconstruction demand for high image feature extraction performance and have a heavily constrained energy budget unable to be met by general-purpose CPUs and GPUs. Due to the required programming flexibility for software updates and algorithmic extensions, the use of fully dedicated hardware accelerators is not advisable in most cases. In this paper, a vertical and a horizontal SIMD vector processor architecture are implemented and compared for accelerating the Scale-Invariant Feature Transform feature extraction algorithm, exploiting inherent data-level parallelism prevalent in this application and considering different programming code strategies for the different vectorization paradigms. An evaluation for a 45 nm ASIC technology shows an overall performance gain of up to 24.8x, and up to 151.3x higher total performance-area-energy efficiency compared to a reference scalar two-issue VLIW processor. Compared to other implementations on programmable ASIP and mobile GPU platforms, the proposed vertical SIMD vector processor achieves a performance gain of up to 5.1x and up to 31.3x higher performance-energy efficiency.
Keywords
- Application-Specific processor, Computer vision, Feature extraction, Scale-Invariant feature transform, SIMD, Vector processing
ASJC Scopus subject areas
- Computer Science(all)
- Software
- Computer Science(all)
- Hardware and Architecture
Sustainable Development Goals
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In: Journal of Systems Architecture, Vol. 100, 101647, 07.11.2019.
Research output: Contribution to journal › Article › Research › peer review
}
TY - JOUR
T1 - Comparing vertical and horizontal SIMD vector processor architectures for accelerated image feature extraction
AU - Weißbrich, Moritz
AU - García-Ortiz, A.
AU - Payá-Vayá, Guillermo
N1 - Funding information: This work was partly funded by the German Research Council (DFG) under project number PA 2762/1-1.
PY - 2019/11/7
Y1 - 2019/11/7
N2 - Embedded automotive Computer Vision systems for real-time motion tracking and 3D scene reconstruction demand for high image feature extraction performance and have a heavily constrained energy budget unable to be met by general-purpose CPUs and GPUs. Due to the required programming flexibility for software updates and algorithmic extensions, the use of fully dedicated hardware accelerators is not advisable in most cases. In this paper, a vertical and a horizontal SIMD vector processor architecture are implemented and compared for accelerating the Scale-Invariant Feature Transform feature extraction algorithm, exploiting inherent data-level parallelism prevalent in this application and considering different programming code strategies for the different vectorization paradigms. An evaluation for a 45 nm ASIC technology shows an overall performance gain of up to 24.8x, and up to 151.3x higher total performance-area-energy efficiency compared to a reference scalar two-issue VLIW processor. Compared to other implementations on programmable ASIP and mobile GPU platforms, the proposed vertical SIMD vector processor achieves a performance gain of up to 5.1x and up to 31.3x higher performance-energy efficiency.
AB - Embedded automotive Computer Vision systems for real-time motion tracking and 3D scene reconstruction demand for high image feature extraction performance and have a heavily constrained energy budget unable to be met by general-purpose CPUs and GPUs. Due to the required programming flexibility for software updates and algorithmic extensions, the use of fully dedicated hardware accelerators is not advisable in most cases. In this paper, a vertical and a horizontal SIMD vector processor architecture are implemented and compared for accelerating the Scale-Invariant Feature Transform feature extraction algorithm, exploiting inherent data-level parallelism prevalent in this application and considering different programming code strategies for the different vectorization paradigms. An evaluation for a 45 nm ASIC technology shows an overall performance gain of up to 24.8x, and up to 151.3x higher total performance-area-energy efficiency compared to a reference scalar two-issue VLIW processor. Compared to other implementations on programmable ASIP and mobile GPU platforms, the proposed vertical SIMD vector processor achieves a performance gain of up to 5.1x and up to 31.3x higher performance-energy efficiency.
KW - Application-Specific processor
KW - Computer vision
KW - Feature extraction
KW - Scale-Invariant feature transform
KW - SIMD
KW - Vector processing
UR - http://www.scopus.com/inward/record.url?scp=85073813171&partnerID=8YFLogxK
U2 - 10.1016/j.sysarc.2019.101647
DO - 10.1016/j.sysarc.2019.101647
M3 - Article
AN - SCOPUS:85073813171
VL - 100
JO - Journal of Systems Architecture
JF - Journal of Systems Architecture
SN - 1383-7621
M1 - 101647
ER -