Details
| Original language | English |
|---|---|
| Article number | 8354693 |
| Pages (from-to) | 736-745 |
| Number of pages | 10 |
| Journal | IEEE Journal on Emerging and Selected Topics in Circuits and Systems |
| Volume | 8 |
| Issue number | 4 |
| Publication status | Published - Dec 2018 |
Abstract
Numerous approximate adders have been proposed in the literature in response to the languishing benefits of technology scaling. However, they have been obtained with an ad-hoc and non-systematic methodology which does not fully exploit the design space possibilities. This paper provides a conceptual framework for the systematic design of approximate adders, including hybrid and non-equally segmented approaches as well as more robust error metrics. The framework discriminates the scenarios, where approximate processing does not provide significant benefits from those where it does; in this later case, it aids to obtain optimal configurations for the adders. Experimental results with a commercial technology assess the significant improvements of our systematic approach. Furthermore, a case study with a processor enhanced with an approximate accelerator highlights the usability of the methods.
Keywords
- Approximate adders, Automatic design framework, Computer vision, Error metrics, Generic template
ASJC Scopus subject areas
- Engineering(all)
- Electrical and Electronic Engineering
Sustainable Development Goals
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In: IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Vol. 8, No. 4, 8354693, 12.2018, p. 736-745.
Research output: Contribution to journal › Article › Research › peer review
}
TY - JOUR
T1 - Coherent Design of Hybrid Approximate Adders: Unified Design Framework and Metrics
AU - Najafi, A.
AU - Weißbrich, M.
AU - Payá-Vayá, G.
AU - Garcia-Ortiz, A.
N1 - Funding information: Manuscript received January 5, 2018; revised April 1, 2018; accepted April 29, 2018. Date of publication May 4, 2018; date of current version December 11, 2018. This work was supported by the German Research Foundation under Project GA 763/4-1. This paper was recommended by Guest Editor V. De. (Corresponding author: Ardalan Najafi.) A. Najafi and A. Garcia-Ortiz are with the Institute of Electrodynamics and Microelectronics, University of Bremen, 28359 Bremen, Germany (e-mail: ardalan@item.uni-bremen.de; agarcia@item.uni-bremen.de).
PY - 2018/12
Y1 - 2018/12
N2 - Numerous approximate adders have been proposed in the literature in response to the languishing benefits of technology scaling. However, they have been obtained with an ad-hoc and non-systematic methodology which does not fully exploit the design space possibilities. This paper provides a conceptual framework for the systematic design of approximate adders, including hybrid and non-equally segmented approaches as well as more robust error metrics. The framework discriminates the scenarios, where approximate processing does not provide significant benefits from those where it does; in this later case, it aids to obtain optimal configurations for the adders. Experimental results with a commercial technology assess the significant improvements of our systematic approach. Furthermore, a case study with a processor enhanced with an approximate accelerator highlights the usability of the methods.
AB - Numerous approximate adders have been proposed in the literature in response to the languishing benefits of technology scaling. However, they have been obtained with an ad-hoc and non-systematic methodology which does not fully exploit the design space possibilities. This paper provides a conceptual framework for the systematic design of approximate adders, including hybrid and non-equally segmented approaches as well as more robust error metrics. The framework discriminates the scenarios, where approximate processing does not provide significant benefits from those where it does; in this later case, it aids to obtain optimal configurations for the adders. Experimental results with a commercial technology assess the significant improvements of our systematic approach. Furthermore, a case study with a processor enhanced with an approximate accelerator highlights the usability of the methods.
KW - Approximate adders
KW - Automatic design framework
KW - Computer vision
KW - Error metrics
KW - Generic template
UR - http://www.scopus.com/inward/record.url?scp=85046429017&partnerID=8YFLogxK
U2 - 10.1109/jetcas.2018.2833284
DO - 10.1109/jetcas.2018.2833284
M3 - Article
VL - 8
SP - 736
EP - 745
JO - IEEE Journal on Emerging and Selected Topics in Circuits and Systems
JF - IEEE Journal on Emerging and Selected Topics in Circuits and Systems
SN - 2156-3357
IS - 4
M1 - 8354693
ER -