Details
| Original language | English |
|---|---|
| Title of host publication | Proceedings |
| Subtitle of host publication | 13th IEEE International Workshop on Rapid System Prototyping, RSP 2002 |
| Publisher | IEEE Computer Society |
| Pages | 60-65 |
| Number of pages | 6 |
| ISBN (electronic) | 076951703X |
| Publication status | Published - 2002 |
| Event | 13th IEEE International Workshop on Rapid System Prototyping, RSP 2002 - Darmstadt, Germany Duration: 1 Jul 2002 → 3 Jul 2002 |
Publication series
| Name | Proceedings of the International Workshop on Rapid System Prototyping |
|---|---|
| Volume | 2002-January |
| ISSN (Print) | 1074-6005 |
Abstract
Large rapid-prototyping systems comprising several FPGAs become more and more the tool at hand to verify complete hardware systems at an early stage of development for first time success. Although hardware capability is growing rapidly the appropriate software tools are lacking in mapping performance and quality. It is especially difficult to meet certain real-time constraints when a design is distributed among several FPGAs. We propose a macro-based partitioning methodology that significantly improves turnaround times and leads to very compact hardware realizations. We demonstrate the benefits of our approach for a real-time video processing application. In addition, compilation time and hardware resources could be reduced by 35% and 45%, respectively.
Keywords
- Circuit simulation, Emulation, Field programmable gate arrays, Hardware, Image processing, Prototypes, Real time systems, Signal processing algorithms, Software prototyping, Throughput
ASJC Scopus subject areas
- Computer Science(all)
- General Computer Science
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Proceedings : 13th IEEE International Workshop on Rapid System Prototyping, RSP 2002. IEEE Computer Society, 2002. p. 60-65 1029739 (Proceedings of the International Workshop on Rapid System Prototyping; Vol. 2002-January).
Research output: Chapter in book/report/conference proceeding › Conference contribution › Research › peer review
}
TY - GEN
T1 - Benefits of macro-based multi-FPGA partitioning for video processing applications
AU - Martín-Langerwerf, J.
AU - Reuter, C.
AU - Kropp, H.
AU - Pirsch, P.
PY - 2002
Y1 - 2002
N2 - Large rapid-prototyping systems comprising several FPGAs become more and more the tool at hand to verify complete hardware systems at an early stage of development for first time success. Although hardware capability is growing rapidly the appropriate software tools are lacking in mapping performance and quality. It is especially difficult to meet certain real-time constraints when a design is distributed among several FPGAs. We propose a macro-based partitioning methodology that significantly improves turnaround times and leads to very compact hardware realizations. We demonstrate the benefits of our approach for a real-time video processing application. In addition, compilation time and hardware resources could be reduced by 35% and 45%, respectively.
AB - Large rapid-prototyping systems comprising several FPGAs become more and more the tool at hand to verify complete hardware systems at an early stage of development for first time success. Although hardware capability is growing rapidly the appropriate software tools are lacking in mapping performance and quality. It is especially difficult to meet certain real-time constraints when a design is distributed among several FPGAs. We propose a macro-based partitioning methodology that significantly improves turnaround times and leads to very compact hardware realizations. We demonstrate the benefits of our approach for a real-time video processing application. In addition, compilation time and hardware resources could be reduced by 35% and 45%, respectively.
KW - Circuit simulation
KW - Emulation
KW - Field programmable gate arrays
KW - Hardware
KW - Image processing
KW - Prototypes
KW - Real time systems
KW - Signal processing algorithms
KW - Software prototyping
KW - Throughput
UR - http://www.scopus.com/inward/record.url?scp=52949094859&partnerID=8YFLogxK
U2 - 10.1109/IWRSP.2002.1029739
DO - 10.1109/IWRSP.2002.1029739
M3 - Conference contribution
AN - SCOPUS:52949094859
T3 - Proceedings of the International Workshop on Rapid System Prototyping
SP - 60
EP - 65
BT - Proceedings
PB - IEEE Computer Society
T2 - 13th IEEE International Workshop on Rapid System Prototyping, RSP 2002
Y2 - 1 July 2002 through 3 July 2002
ER -