Details
| Original language | English |
|---|---|
| Pages (from-to) | 1887-1890 |
| Number of pages | 4 |
| Journal | Proceedings - IEEE International Symposium on Circuits and Systems |
| Volume | 3 |
| Publication status | Published - 1989 |
| Event | IEEE International Symposium on Circuits and Systems 1989, the 22nd ISCAS. Part 1 - Portland, United States Duration: 8 May 1989 → 11 May 1989 |
Abstract
The CAD tool BADGE, which supports the system designer dealing with CMOS cell libraries, is presented. It provides a library database of alternative schemes for building blocks like adders, multipliers, etc., which are characterized by architecture-describing parameters. BADGE guides the selection of the appropriate scheme and generates the netlist exploiting a given cell library. Although an expert system shell is used to implement the BADGE system, the performance on a μVAXII is sufficient to generate a building block in a reasonable time. It takes about 3 min to create the netlist of an 8-bit fast-carry chain adder and about 5 min for an 8-bit braun-array multiplier consisting of 250 and 870 gates, respectively.
ASJC Scopus subject areas
- Engineering(all)
- Electrical and Electronic Engineering
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In: Proceedings - IEEE International Symposium on Circuits and Systems, Vol. 3, 1989, p. 1887-1890.
Research output: Contribution to journal › Conference article › Research › peer review
}
TY - JOUR
T1 - BADGE
T2 - IEEE International Symposium on Circuits and Systems 1989, the 22nd ISCAS. Part 1
AU - Munzner, Andreas
AU - Pirsch, Peter
PY - 1989
Y1 - 1989
N2 - The CAD tool BADGE, which supports the system designer dealing with CMOS cell libraries, is presented. It provides a library database of alternative schemes for building blocks like adders, multipliers, etc., which are characterized by architecture-describing parameters. BADGE guides the selection of the appropriate scheme and generates the netlist exploiting a given cell library. Although an expert system shell is used to implement the BADGE system, the performance on a μVAXII is sufficient to generate a building block in a reasonable time. It takes about 3 min to create the netlist of an 8-bit fast-carry chain adder and about 5 min for an 8-bit braun-array multiplier consisting of 250 and 870 gates, respectively.
AB - The CAD tool BADGE, which supports the system designer dealing with CMOS cell libraries, is presented. It provides a library database of alternative schemes for building blocks like adders, multipliers, etc., which are characterized by architecture-describing parameters. BADGE guides the selection of the appropriate scheme and generates the netlist exploiting a given cell library. Although an expert system shell is used to implement the BADGE system, the performance on a μVAXII is sufficient to generate a building block in a reasonable time. It takes about 3 min to create the netlist of an 8-bit fast-carry chain adder and about 5 min for an 8-bit braun-array multiplier consisting of 250 and 870 gates, respectively.
UR - http://www.scopus.com/inward/record.url?scp=0024908468&partnerID=8YFLogxK
M3 - Conference article
AN - SCOPUS:0024908468
VL - 3
SP - 1887
EP - 1890
JO - Proceedings - IEEE International Symposium on Circuits and Systems
JF - Proceedings - IEEE International Symposium on Circuits and Systems
SN - 0271-4310
Y2 - 8 May 1989 through 11 May 1989
ER -