Details
| Original language | English |
|---|---|
| Title of host publication | Embedded Computer Systems |
| Subtitle of host publication | Architectures, Modeling, and Simulation - 8th International Workshop, SAMOS 2008, Proceedings |
| Editors | M. Bereković, N. Dimopoulos, S. Wong |
| Publisher | Springer Verlag |
| Pages | 136-145 |
| Number of pages | 10 |
| ISBN (electronic) | 978-3-540-70550-5 |
| ISBN (print) | 354070549X, 9783540705499 |
| Publication status | Published - 2008 |
| Externally published | Yes |
| Event | 8th International Workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS 2008 - Samos, Greece Duration: 21 Jul 2008 → 24 Jul 2008 |
Publication series
| Name | Lecture Notes in Computer Science (LNCS) |
|---|---|
| Volume | 5114 |
| ISSN (Print) | 0302-9743 |
| ISSN (electronic) | 1611-3349 |
Abstract
In this paper a novel flexible architecture exemplarily applied for multioperable GNSS receivers including an ASIP and an arithmetic oriented embedded FPGA is presented. The advent of next generation GNSS-systems as well as different demands in different system phases require high flexibility. The proposed architecture provides high energy and area efficiency compared to software-programmable processor while preserving flexibility. Exemplarily the mapping of the computational intensive base band processing of a Navstar GPS receiver to an ASIP-eFPGA architecture will be discussed. Results are based on a standard cell based design regarding the ASIP. A design method for physically optimized VLSI-macros has been applied for the implementation of the eFPGA. All results are acquired for a 90 nm-CMOS technology. It will be shown that the proposed heterogeneous architecture features an attractive position in the design space regarding area and energy efficiency as well as flexibility.
Keywords
- Arithmetic oriented eFPGA, ASIP, Multioperable GNSS
ASJC Scopus subject areas
- Mathematics(all)
- Theoretical Computer Science
- Computer Science(all)
- General Computer Science
Sustainable Development Goals
Cite this
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- BibTeX
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Embedded Computer Systems: Architectures, Modeling, and Simulation - 8th International Workshop, SAMOS 2008, Proceedings. ed. / M. Bereković; N. Dimopoulos; S. Wong. Springer Verlag, 2008. p. 136-145 (Lecture Notes in Computer Science (LNCS); Vol. 5114).
Research output: Chapter in book/report/conference proceeding › Conference contribution › Research › peer review
}
TY - GEN
T1 - ASIP-eFPGA Architecture for Multioperable GNSS Receivers
AU - Von Sydow, Thorsten
AU - Blume, Holger
AU - Kappen, Götz
AU - Noll, Tobias G.
PY - 2008
Y1 - 2008
N2 - In this paper a novel flexible architecture exemplarily applied for multioperable GNSS receivers including an ASIP and an arithmetic oriented embedded FPGA is presented. The advent of next generation GNSS-systems as well as different demands in different system phases require high flexibility. The proposed architecture provides high energy and area efficiency compared to software-programmable processor while preserving flexibility. Exemplarily the mapping of the computational intensive base band processing of a Navstar GPS receiver to an ASIP-eFPGA architecture will be discussed. Results are based on a standard cell based design regarding the ASIP. A design method for physically optimized VLSI-macros has been applied for the implementation of the eFPGA. All results are acquired for a 90 nm-CMOS technology. It will be shown that the proposed heterogeneous architecture features an attractive position in the design space regarding area and energy efficiency as well as flexibility.
AB - In this paper a novel flexible architecture exemplarily applied for multioperable GNSS receivers including an ASIP and an arithmetic oriented embedded FPGA is presented. The advent of next generation GNSS-systems as well as different demands in different system phases require high flexibility. The proposed architecture provides high energy and area efficiency compared to software-programmable processor while preserving flexibility. Exemplarily the mapping of the computational intensive base band processing of a Navstar GPS receiver to an ASIP-eFPGA architecture will be discussed. Results are based on a standard cell based design regarding the ASIP. A design method for physically optimized VLSI-macros has been applied for the implementation of the eFPGA. All results are acquired for a 90 nm-CMOS technology. It will be shown that the proposed heterogeneous architecture features an attractive position in the design space regarding area and energy efficiency as well as flexibility.
KW - Arithmetic oriented eFPGA
KW - ASIP
KW - Multioperable GNSS
UR - http://www.scopus.com/inward/record.url?scp=50649085934&partnerID=8YFLogxK
U2 - 10.1007/978-3-540-70550-5_15
DO - 10.1007/978-3-540-70550-5_15
M3 - Conference contribution
AN - SCOPUS:50649085934
SN - 354070549X
SN - 9783540705499
T3 - Lecture Notes in Computer Science (LNCS)
SP - 136
EP - 145
BT - Embedded Computer Systems
A2 - Bereković, M.
A2 - Dimopoulos, N.
A2 - Wong, S.
PB - Springer Verlag
T2 - 8th International Workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS 2008
Y2 - 21 July 2008 through 24 July 2008
ER -