Array Architectures for Block Matching Algorithms

Research output: Contribution to journal › Article › Research › peer review

Authors

  • Thomas Komarek
  • Peter Pirsch

Research Organisations

View graph of relations

Details

Original languageEnglish
Pages (from-to)1301-1308
Number of pages8
JournalIEEE Transactions on Circuits and Systems
Volume36
Issue number10
Publication statusPublished - Oct 1989

Abstract

This paper describes VLSI-architectures of block matching algorithms (BMA's) utilizing systolic array processors. A well-known mapping procedure has been applied to derive the array processors from the algorithm. Examples of two- and one-dimensional systolic arrays are presented. The transistor-count of the architectures using presently available CMOS technology and their maximum processable frame rates for real-time computation of video signals have been estimated.

ASJC Scopus subject areas

Cite this

Array Architectures for Block Matching Algorithms. / Komarek, Thomas; Pirsch, Peter.
In: IEEE Transactions on Circuits and Systems, Vol. 36, No. 10, 10.1989, p. 1301-1308.

Research output: Contribution to journal › Article › Research › peer review

Komarek T, Pirsch P. Array Architectures for Block Matching Algorithms. IEEE Transactions on Circuits and Systems. 1989 Oct;36(10):1301-1308. doi: 10.1109/31.44346
Komarek, Thomas ; Pirsch, Peter. / Array Architectures for Block Matching Algorithms. In: IEEE Transactions on Circuits and Systems. 1989 ; Vol. 36, No. 10. pp. 1301-1308.
Download
@article{85f4cc8088bd41c6a07fd06c666bc0b6,
title = "Array Architectures for Block Matching Algorithms",
abstract = "This paper describes VLSI-architectures of block matching algorithms (BMA's) utilizing systolic array processors. A well-known mapping procedure has been applied to derive the array processors from the algorithm. Examples of two- and one-dimensional systolic arrays are presented. The transistor-count of the architectures using presently available CMOS technology and their maximum processable frame rates for real-time computation of video signals have been estimated.",
author = "Thomas Komarek and Peter Pirsch",
year = "1989",
month = oct,
doi = "10.1109/31.44346",
language = "English",
volume = "36",
pages = "1301--1308",
journal = "IEEE Transactions on Circuits and Systems",
issn = "0098-4094",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "10",

}

Download

TY - JOUR

T1 - Array Architectures for Block Matching Algorithms

AU - Komarek, Thomas

AU - Pirsch, Peter

PY - 1989/10

Y1 - 1989/10

N2 - This paper describes VLSI-architectures of block matching algorithms (BMA's) utilizing systolic array processors. A well-known mapping procedure has been applied to derive the array processors from the algorithm. Examples of two- and one-dimensional systolic arrays are presented. The transistor-count of the architectures using presently available CMOS technology and their maximum processable frame rates for real-time computation of video signals have been estimated.

AB - This paper describes VLSI-architectures of block matching algorithms (BMA's) utilizing systolic array processors. A well-known mapping procedure has been applied to derive the array processors from the algorithm. Examples of two- and one-dimensional systolic arrays are presented. The transistor-count of the architectures using presently available CMOS technology and their maximum processable frame rates for real-time computation of video signals have been estimated.

UR - http://www.scopus.com/inward/record.url?scp=0024753317&partnerID=8YFLogxK

U2 - 10.1109/31.44346

DO - 10.1109/31.44346

M3 - Article

AN - SCOPUS:0024753317

VL - 36

SP - 1301

EP - 1308

JO - IEEE Transactions on Circuits and Systems

JF - IEEE Transactions on Circuits and Systems

SN - 0098-4094

IS - 10

ER -