Architecture of an image rendering co-processor for MPEG-4 visual compositing

Research output: Contribution to journal › Article › Research › peer review

Authors

  • M. Berekovic
  • P. Pirsch
  • T. Selinger
  • K. I. Wels
  • C. Miro
  • A. Lafage
  • C. Heer
  • G. Ghigo

Research Organisations

External Research Organisations

  • Fraunhofer Institute for Telecommunications, Heinrich Hertz Institute (HHI)
  • Télécom ParisTech
  • Infineon Technologies AG
  • Centro Studi e Laboratori Telecomunicazioni (CSELT)
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Details

Original languageEnglish
Pages (from-to)157-171
Number of pages15
JournalJournal of VLSI Signal Processing Systems for Signal, Image, and Video Technology
Volume31
Issue number2
Publication statusPublished - 1 Jul 2002

Abstract

The TANGRAM VLSI co-processor is intended as a building block for use in system-on-chip (SOC) designs for the versatile MPEG-4 multimedia standard. It is designed to perform the computation intensive final step of MPEG-4 video decoding: compositing of scenes at the display. This includes warping and alpha blending of multiple full-screen video textures in real-time. TANGRAM consists of a RISC control processor and multiple powerful arithmetic units that perform rendering calculations directly in hardware. This hybrid architecture enables adaptation to changes in algorithms or support for different video-formats in software. Communication to a host CPU and video decoding hardware is done via the very common PI-bus on-chip interface. TANGRAM directly interfaces with the ITU-R601/656 digital video output. VHDL implementation and synthesis for a 0.35 μ standardcell library provide an estimate of 100 MHz achievable clock frequency (worst-case), 52 mm2 overall area and 1 Watt power dissipation. TANGRAM has sufficient performance for rendering of MPEG-4 Main Profile@Layer3 scenes (ITU-R 601).

Keywords

    Blending, Compositing, MPEG-4 main profile, Sprites, Video object plane (VOP), Warping

ASJC Scopus subject areas

Cite this

Architecture of an image rendering co-processor for MPEG-4 visual compositing. / Berekovic, M.; Pirsch, P.; Selinger, T. et al.
In: Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, Vol. 31, No. 2, 01.07.2002, p. 157-171.

Research output: Contribution to journal › Article › Research › peer review

Berekovic M, Pirsch P, Selinger T, Wels KI, Miro C, Lafage A et al. Architecture of an image rendering co-processor for MPEG-4 visual compositing. Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology. 2002 Jul 1;31(2):157-171. doi: 10.1023/A:1015345406334
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