Details
| Original language | English |
|---|---|
| Title of host publication | Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 203-206 |
| Number of pages | 4 |
| ISBN (electronic) | 0780350081 |
| Publication status | Published - 1998 |
| Event | 5th IEEE International Conference on Electronics, Circuits and Systems, ICECS 1998 - Lisboa, Portugal Duration: 7 Sept 1998 → 10 Sept 1998 |
Publication series
| Name | Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems |
|---|---|
| Volume | 2 |
Abstract
This paper proposes the architecture of a coprocesssor module for image compositing. The emerging MPEG-4 standard for multimedia applications allows script-based compositing of audiovisual scenes from multiple audio and visual objects. This involves the composition of the output frame by alpha-blending of Video Object Planes (VOPs). A coprocessor architecture is presented, that works in parallel to an MPEG-4 video-and audio-decoder, and performs computation and bandwidth intensive low-level algorithms for image compositing. The processor has on-chip memories that allow preload of data before it is accessed. VHDL implementation and synthesis for a 0.5μ process show an estimate of 100 MHz achievable clock-frequency and 10 k gates for arithmetic and control circuitry which results in roughly 5 mm2 silicon area. Overall performance is sufficient to compose more than 5 full-screen VOPs with a background of size 704×576 each at 30 Hz.
ASJC Scopus subject areas
- Engineering(all)
- Electrical and Electronic Engineering
- Engineering(all)
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Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems. Institute of Electrical and Electronics Engineers Inc., 1998. p. 203-206 814863 (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems; Vol. 2).
Research output: Chapter in book/report/conference proceeding › Conference contribution › Research › peer review
}
TY - GEN
T1 - Architecture of a coprocessor module for image compositing
AU - Berekovic, Mladen
AU - Pirsch, Peter
PY - 1998
Y1 - 1998
N2 - This paper proposes the architecture of a coprocesssor module for image compositing. The emerging MPEG-4 standard for multimedia applications allows script-based compositing of audiovisual scenes from multiple audio and visual objects. This involves the composition of the output frame by alpha-blending of Video Object Planes (VOPs). A coprocessor architecture is presented, that works in parallel to an MPEG-4 video-and audio-decoder, and performs computation and bandwidth intensive low-level algorithms for image compositing. The processor has on-chip memories that allow preload of data before it is accessed. VHDL implementation and synthesis for a 0.5μ process show an estimate of 100 MHz achievable clock-frequency and 10 k gates for arithmetic and control circuitry which results in roughly 5 mm2 silicon area. Overall performance is sufficient to compose more than 5 full-screen VOPs with a background of size 704×576 each at 30 Hz.
AB - This paper proposes the architecture of a coprocesssor module for image compositing. The emerging MPEG-4 standard for multimedia applications allows script-based compositing of audiovisual scenes from multiple audio and visual objects. This involves the composition of the output frame by alpha-blending of Video Object Planes (VOPs). A coprocessor architecture is presented, that works in parallel to an MPEG-4 video-and audio-decoder, and performs computation and bandwidth intensive low-level algorithms for image compositing. The processor has on-chip memories that allow preload of data before it is accessed. VHDL implementation and synthesis for a 0.5μ process show an estimate of 100 MHz achievable clock-frequency and 10 k gates for arithmetic and control circuitry which results in roughly 5 mm2 silicon area. Overall performance is sufficient to compose more than 5 full-screen VOPs with a background of size 704×576 each at 30 Hz.
UR - http://www.scopus.com/inward/record.url?scp=0032269347&partnerID=8YFLogxK
U2 - 10.1109/ICECS.1998.814863
DO - 10.1109/ICECS.1998.814863
M3 - Conference contribution
AN - SCOPUS:0032269347
T3 - Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems
SP - 203
EP - 206
BT - Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 5th IEEE International Conference on Electronics, Circuits and Systems, ICECS 1998
Y2 - 7 September 1998 through 10 September 1998
ER -