Architecture and VLSI implementation of a RISC core for a monolithic video signal processor

Research output: Contribution to conference › Paper › Research › peer review

Authors

  • Klaus Herrmann
  • Martin Seifert
  • Klaus Gaedke
  • Hartwig Jeschke
  • Peter Pirsch

Research Organisations

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Details

Original languageEnglish
Pages368-377
Number of pages10
Publication statusPublished - 1994
Event1994 IEEE International Workshop VLSI Signal Processing - La Jolla, CA, USA
Duration: 26 Oct 1994 → 28 Oct 1994

Conference

Conference1994 IEEE International Workshop VLSI Signal Processing
CityLa Jolla, CA, USA
Period26 Oct 1994 → 28 Oct 1994

Abstract

For a monolithic video signal processor a special RISC processor core has been developed. In order to achieve an efficient implementation of hybrid video coding algorithms the applied Harvard architecture with 16 bit data path is adapted to tasks like quantization, variable length coding and run length coding. The RISC processor's die size is 68.79 mm2 fabricated in a 0.8 μm CMOS technology. 4 kByte of program RAM and 512 Bytes of Data Memory are implemented on chip. The operating frequency is 66 MHz.

ASJC Scopus subject areas

Cite this

Architecture and VLSI implementation of a RISC core for a monolithic video signal processor. / Herrmann, Klaus; Seifert, Martin; Gaedke, Klaus et al.
1994. 368-377 Paper presented at 1994 IEEE International Workshop VLSI Signal Processing, La Jolla, CA, USA.

Research output: Contribution to conference › Paper › Research › peer review

Herrmann, K, Seifert, M, Gaedke, K, Jeschke, H & Pirsch, P 1994, 'Architecture and VLSI implementation of a RISC core for a monolithic video signal processor', Paper presented at 1994 IEEE International Workshop VLSI Signal Processing, La Jolla, CA, USA, 26 Oct 1994 - 28 Oct 1994 pp. 368-377.
Herrmann, K., Seifert, M., Gaedke, K., Jeschke, H., & Pirsch, P. (1994). Architecture and VLSI implementation of a RISC core for a monolithic video signal processor. 368-377. Paper presented at 1994 IEEE International Workshop VLSI Signal Processing, La Jolla, CA, USA.
Herrmann K, Seifert M, Gaedke K, Jeschke H, Pirsch P. Architecture and VLSI implementation of a RISC core for a monolithic video signal processor. 1994. Paper presented at 1994 IEEE International Workshop VLSI Signal Processing, La Jolla, CA, USA.
Herrmann, Klaus ; Seifert, Martin ; Gaedke, Klaus et al. / Architecture and VLSI implementation of a RISC core for a monolithic video signal processor. Paper presented at 1994 IEEE International Workshop VLSI Signal Processing, La Jolla, CA, USA.10 p.
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