Application of global loops on ULSI routing for DfY

Research output: Chapter in book/report/conference proceedingConference contributionResearchpeer review

Authors

  • P. Panitz
  • M. Olbrich
  • J. Koehl
  • E. Barke

Research Organisations

External Research Organisations

  • IBM
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Details

Original languageEnglish
Title of host publication2006 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT'06
PublisherIEEE Computer Society
ISBN (print)1424400988, 9781424400980
Publication statusPublished - 2006
Event Integrated Circuit Design and Technology, 2006. ICICDT '06. 2006 IEEE International Conference - Padova, Italy
Duration: 24 May 200626 May 2006

Abstract

The number of circuit malfunctions due to opens increases with shrinking technologies. This requires to reconsider traditional tree based routing approaches for signal wiring. In this paper, we apply global loops to generate robust net topologies which are fully immune against single open faults. We show that the solution of the travelling salesperson problem yields a nearly optimal solution to the two edge connected subgraph problem. Additionally, we introduce a heuristic for finding additional segments which significantly reduce the delay. As result the critical area reduction is better than in previous published approaches which augment minimum Steiner trees.

ASJC Scopus subject areas

Cite this

Application of global loops on ULSI routing for DfY. / Panitz, P.; Olbrich, M.; Koehl, J. et al.
2006 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT'06. IEEE Computer Society, 2006. 1669409.

Research output: Chapter in book/report/conference proceedingConference contributionResearchpeer review

Panitz, P, Olbrich, M, Koehl, J & Barke, E 2006, Application of global loops on ULSI routing for DfY. in 2006 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT'06., 1669409, IEEE Computer Society, Integrated Circuit Design and Technology, 2006. ICICDT '06. 2006 IEEE International Conference, Padova, Italy, 24 May 2006. https://doi.org/10.1109/icicdt.2006.220822
Panitz, P., Olbrich, M., Koehl, J., & Barke, E. (2006). Application of global loops on ULSI routing for DfY. In 2006 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT'06 Article 1669409 IEEE Computer Society. https://doi.org/10.1109/icicdt.2006.220822
Panitz P, Olbrich M, Koehl J, Barke E. Application of global loops on ULSI routing for DfY. In 2006 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT'06. IEEE Computer Society. 2006. 1669409 doi: 10.1109/icicdt.2006.220822
Panitz, P. ; Olbrich, M. ; Koehl, J. et al. / Application of global loops on ULSI routing for DfY. 2006 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT'06. IEEE Computer Society, 2006.
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@inproceedings{52ab7496d0614cdba95e683f247eed01,
title = "Application of global loops on ULSI routing for DfY",
abstract = "The number of circuit malfunctions due to opens increases with shrinking technologies. This requires to reconsider traditional tree based routing approaches for signal wiring. In this paper, we apply global loops to generate robust net topologies which are fully immune against single open faults. We show that the solution of the travelling salesperson problem yields a nearly optimal solution to the two edge connected subgraph problem. Additionally, we introduce a heuristic for finding additional segments which significantly reduce the delay. As result the critical area reduction is better than in previous published approaches which augment minimum Steiner trees.",
author = "P. Panitz and M. Olbrich and J. Koehl and E. Barke",
year = "2006",
doi = "10.1109/icicdt.2006.220822",
language = "English",
isbn = "1424400988",
booktitle = "2006 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT'06",
publisher = "IEEE Computer Society",
address = "United States",
note = " Integrated Circuit Design and Technology, 2006. ICICDT '06. 2006 IEEE International Conference ; Conference date: 24-05-2006 Through 26-05-2006",

}

Download

TY - GEN

T1 - Application of global loops on ULSI routing for DfY

AU - Panitz, P.

AU - Olbrich, M.

AU - Koehl, J.

AU - Barke, E.

PY - 2006

Y1 - 2006

N2 - The number of circuit malfunctions due to opens increases with shrinking technologies. This requires to reconsider traditional tree based routing approaches for signal wiring. In this paper, we apply global loops to generate robust net topologies which are fully immune against single open faults. We show that the solution of the travelling salesperson problem yields a nearly optimal solution to the two edge connected subgraph problem. Additionally, we introduce a heuristic for finding additional segments which significantly reduce the delay. As result the critical area reduction is better than in previous published approaches which augment minimum Steiner trees.

AB - The number of circuit malfunctions due to opens increases with shrinking technologies. This requires to reconsider traditional tree based routing approaches for signal wiring. In this paper, we apply global loops to generate robust net topologies which are fully immune against single open faults. We show that the solution of the travelling salesperson problem yields a nearly optimal solution to the two edge connected subgraph problem. Additionally, we introduce a heuristic for finding additional segments which significantly reduce the delay. As result the critical area reduction is better than in previous published approaches which augment minimum Steiner trees.

UR - http://www.scopus.com/inward/record.url?scp=37649026512&partnerID=8YFLogxK

U2 - 10.1109/icicdt.2006.220822

DO - 10.1109/icicdt.2006.220822

M3 - Conference contribution

AN - SCOPUS:37649026512

SN - 1424400988

SN - 9781424400980

BT - 2006 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT'06

PB - IEEE Computer Society

T2 - Integrated Circuit Design and Technology, 2006. ICICDT '06. 2006 IEEE International Conference

Y2 - 24 May 2006 through 26 May 2006

ER -