Details
| Original language | English |
|---|---|
| Title of host publication | Proceedings of the 27th European Solid-State Circuits Conference |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 409-412 |
| Number of pages | 4 |
| Publication status | Published - 2001 |
| Externally published | Yes |
Abstract
Optimum partitioning plays a crucial role in the implementation of systems on heterogeneous target architectures. Typical target architectures for such systems include FPGAs, semi-custom or physically optimized ASICs as well as programmable digital signal or general purpose processors. The goal was to provide an estimation for implementation specific parameters like throughput rate, power dissipation and required silicon area by means of cost functions. Considering normalization we provide implementation parameters of selected basic operations like linear and nonlinear filtering, exemplary arithmetic operation and simple matching operations which all are required in the digital video processing domain. These operations were optimized for each architecture block. We show quantitatively that the cost ratio between different architecture blocks highly depends on the operation to be performed. This information is essential in order to find the optimum partitioning for implementing a system.
ASJC Scopus subject areas
- Computer Science(all)
- Hardware and Architecture
- Engineering(all)
- Electrical and Electronic Engineering
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Proceedings of the 27th European Solid-State Circuits Conference. Institute of Electrical and Electronics Engineers Inc., 2001. p. 409-412 1371420.
Research output: Chapter in book/report/conference proceeding › Conference contribution › Research › peer review
}
TY - GEN
T1 - Analyzing heterogeneous system architectures by means of cost functions
T2 - A comparative study for basic operations
AU - Blume, H.
AU - Feldkämper, H. T.
AU - Hubert, H.
AU - Noll, T. G.
PY - 2001
Y1 - 2001
N2 - Optimum partitioning plays a crucial role in the implementation of systems on heterogeneous target architectures. Typical target architectures for such systems include FPGAs, semi-custom or physically optimized ASICs as well as programmable digital signal or general purpose processors. The goal was to provide an estimation for implementation specific parameters like throughput rate, power dissipation and required silicon area by means of cost functions. Considering normalization we provide implementation parameters of selected basic operations like linear and nonlinear filtering, exemplary arithmetic operation and simple matching operations which all are required in the digital video processing domain. These operations were optimized for each architecture block. We show quantitatively that the cost ratio between different architecture blocks highly depends on the operation to be performed. This information is essential in order to find the optimum partitioning for implementing a system.
AB - Optimum partitioning plays a crucial role in the implementation of systems on heterogeneous target architectures. Typical target architectures for such systems include FPGAs, semi-custom or physically optimized ASICs as well as programmable digital signal or general purpose processors. The goal was to provide an estimation for implementation specific parameters like throughput rate, power dissipation and required silicon area by means of cost functions. Considering normalization we provide implementation parameters of selected basic operations like linear and nonlinear filtering, exemplary arithmetic operation and simple matching operations which all are required in the digital video processing domain. These operations were optimized for each architecture block. We show quantitatively that the cost ratio between different architecture blocks highly depends on the operation to be performed. This information is essential in order to find the optimum partitioning for implementing a system.
UR - http://www.scopus.com/inward/record.url?scp=84893658320&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:84893658320
SP - 409
EP - 412
BT - Proceedings of the 27th European Solid-State Circuits Conference
PB - Institute of Electrical and Electronics Engineers Inc.
ER -