Analysis and compensation of the bitline multiplexer in SRAM current sense amplifiers

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External Research Organisations

  • Technical University of Munich (TUM)
  • Institute of Electrical and Electronics Engineers (IEEE)
  • Infineon Technologies AG
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Details

Original languageEnglish
Pages (from-to)1745-1755
Number of pages11
JournalIEEE Journal of Solid-State Circuits
Volume36
Issue number11
Publication statusPublished - Nov 2001
Externally publishedYes

Abstract

Current sensing in SRAMs is very promising to achieve high-speed operation in low-voltage applications. However, so far, a main limitation of the practical use of current sense amplifiers is the finite resistance of the bitline multiplexer (MUX). In this paper, the MUX itself and its influence on two types of current sense amplifiers is analyzed. It is shown that the MUX causes a significant performance degradation. A principle is presented to compensate for the bitline multiplexer by means of a current sense amplifier with improved feedback structure. The proposed solution is implemented in a 512 × 24 bit SRAM macro in 0.18-μm 1.8-V CMOS. It is shown by theory and measurements that, using the proposed circuit, it is possible to fully compensate for the MUX in terms of speed and signal amplitude with only little layout area penalty. A speed improvement due to the compensation of typically 0.5 ns is measured.

Keywords

    Bitline multiplexer, Current sense amplifier, Current sensing, MOS transistor switch, Multiplexer compensation, Multiplexer resistance, SRAM circuits

ASJC Scopus subject areas

Cite this

Analysis and compensation of the bitline multiplexer in SRAM current sense amplifiers. / Wicht, Bernhard; Paul, Steffen; Schmitt-Landsiedel, Doris.
In: IEEE Journal of Solid-State Circuits, Vol. 36, No. 11, 11.2001, p. 1745-1755.

Research output: Contribution to journalArticleResearchpeer review

Wicht, Bernhard ; Paul, Steffen ; Schmitt-Landsiedel, Doris. / Analysis and compensation of the bitline multiplexer in SRAM current sense amplifiers. In: IEEE Journal of Solid-State Circuits. 2001 ; Vol. 36, No. 11. pp. 1745-1755.
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@article{671f57f4cfc448f0a8c2ca8efdc8d307,
title = "Analysis and compensation of the bitline multiplexer in SRAM current sense amplifiers",
abstract = "Current sensing in SRAMs is very promising to achieve high-speed operation in low-voltage applications. However, so far, a main limitation of the practical use of current sense amplifiers is the finite resistance of the bitline multiplexer (MUX). In this paper, the MUX itself and its influence on two types of current sense amplifiers is analyzed. It is shown that the MUX causes a significant performance degradation. A principle is presented to compensate for the bitline multiplexer by means of a current sense amplifier with improved feedback structure. The proposed solution is implemented in a 512 × 24 bit SRAM macro in 0.18-μm 1.8-V CMOS. It is shown by theory and measurements that, using the proposed circuit, it is possible to fully compensate for the MUX in terms of speed and signal amplitude with only little layout area penalty. A speed improvement due to the compensation of typically 0.5 ns is measured.",
keywords = "Bitline multiplexer, Current sense amplifier, Current sensing, MOS transistor switch, Multiplexer compensation, Multiplexer resistance, SRAM circuits",
author = "Bernhard Wicht and Steffen Paul and Doris Schmitt-Landsiedel",
year = "2001",
month = nov,
doi = "10.1109/4.962297",
language = "English",
volume = "36",
pages = "1745--1755",
journal = "IEEE Journal of Solid-State Circuits",
issn = "0018-9200",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "11",

}

Download

TY - JOUR

T1 - Analysis and compensation of the bitline multiplexer in SRAM current sense amplifiers

AU - Wicht, Bernhard

AU - Paul, Steffen

AU - Schmitt-Landsiedel, Doris

PY - 2001/11

Y1 - 2001/11

N2 - Current sensing in SRAMs is very promising to achieve high-speed operation in low-voltage applications. However, so far, a main limitation of the practical use of current sense amplifiers is the finite resistance of the bitline multiplexer (MUX). In this paper, the MUX itself and its influence on two types of current sense amplifiers is analyzed. It is shown that the MUX causes a significant performance degradation. A principle is presented to compensate for the bitline multiplexer by means of a current sense amplifier with improved feedback structure. The proposed solution is implemented in a 512 × 24 bit SRAM macro in 0.18-μm 1.8-V CMOS. It is shown by theory and measurements that, using the proposed circuit, it is possible to fully compensate for the MUX in terms of speed and signal amplitude with only little layout area penalty. A speed improvement due to the compensation of typically 0.5 ns is measured.

AB - Current sensing in SRAMs is very promising to achieve high-speed operation in low-voltage applications. However, so far, a main limitation of the practical use of current sense amplifiers is the finite resistance of the bitline multiplexer (MUX). In this paper, the MUX itself and its influence on two types of current sense amplifiers is analyzed. It is shown that the MUX causes a significant performance degradation. A principle is presented to compensate for the bitline multiplexer by means of a current sense amplifier with improved feedback structure. The proposed solution is implemented in a 512 × 24 bit SRAM macro in 0.18-μm 1.8-V CMOS. It is shown by theory and measurements that, using the proposed circuit, it is possible to fully compensate for the MUX in terms of speed and signal amplitude with only little layout area penalty. A speed improvement due to the compensation of typically 0.5 ns is measured.

KW - Bitline multiplexer

KW - Current sense amplifier

KW - Current sensing

KW - MOS transistor switch

KW - Multiplexer compensation

KW - Multiplexer resistance

KW - SRAM circuits

UR - http://www.scopus.com/inward/record.url?scp=0035505539&partnerID=8YFLogxK

U2 - 10.1109/4.962297

DO - 10.1109/4.962297

M3 - Article

AN - SCOPUS:0035505539

VL - 36

SP - 1745

EP - 1755

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

SN - 0018-9200

IS - 11

ER -

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