An SoC with two multimedia DSPs and a RISC core for video compression applications

Research output: Contribution to journal › Conference article › Research › peer review

Authors

  • H. J. Stolberg
  • S. Moch
  • L. Friebe
  • A. Dehnhardt
  • M. B. Kulaczewski
  • M. Berekovic
  • P. Pirsch

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Details

Original languageEnglish
Pages (from-to)330-331+325+531
JournalDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume47
Publication statusPublished - 2004
EventDigest of Technical Papers - 2004 IEEE International Solid-State Circuits Conference - San Francisco, CA., United States
Duration: 15 Feb 2003 → 19 Feb 2003

Abstract

An SoC is comprised of a 16-way SIMD DSP core with a 2D matrix memory, a 64b VLIW DSP core with subword parallelism, and a 32b RISC core. The 81mm 2 chip is implemented in a 0.18μm 6M standard-cell technology and runs at 145MHz. The device can perform MPEG-4 Advanced Simple Profile decoding at D1 resolution, MPEG-4 encoding, and object segmentation in real-time.

ASJC Scopus subject areas

Cite this

An SoC with two multimedia DSPs and a RISC core for video compression applications. / Stolberg, H. J.; Moch, S.; Friebe, L. et al.
In: Digest of Technical Papers - IEEE International Solid-State Circuits Conference, Vol. 47, 2004, p. 330-331+325+531.

Research output: Contribution to journal › Conference article › Research › peer review

Stolberg, HJ, Moch, S, Friebe, L, Dehnhardt, A, Kulaczewski, MB, Berekovic, M & Pirsch, P 2004, 'An SoC with two multimedia DSPs and a RISC core for video compression applications', Digest of Technical Papers - IEEE International Solid-State Circuits Conference, vol. 47, pp. 330-331+325+531.
Stolberg, H. J., Moch, S., Friebe, L., Dehnhardt, A., Kulaczewski, M. B., Berekovic, M., & Pirsch, P. (2004). An SoC with two multimedia DSPs and a RISC core for video compression applications. Digest of Technical Papers - IEEE International Solid-State Circuits Conference, 47, 330-331+325+531.
Stolberg HJ, Moch S, Friebe L, Dehnhardt A, Kulaczewski MB, Berekovic M et al. An SoC with two multimedia DSPs and a RISC core for video compression applications. Digest of Technical Papers - IEEE International Solid-State Circuits Conference. 2004;47:330-331+325+531.
Stolberg, H. J. ; Moch, S. ; Friebe, L. et al. / An SoC with two multimedia DSPs and a RISC core for video compression applications. In: Digest of Technical Papers - IEEE International Solid-State Circuits Conference. 2004 ; Vol. 47. pp. 330-331+325+531.
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