Details
| Original language | English |
|---|---|
| Title of host publication | Proceedings |
| Subtitle of host publication | Computer Graphics International, CGI 1998 |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 411-414 |
| Number of pages | 4 |
| ISBN (electronic) | 0818684453, 9780818684456 |
| Publication status | Published - 1998 |
| Event | 1998 Computer Graphics International, CGI 1998 - Hannover, Germany Duration: 22 Jun 1998 → 26 Jun 1998 |
Publication series
| Name | Proceedings - Computer Graphics International, CGI 1998 |
|---|---|
| Volume | 1998-January |
Abstract
This paper proposes a new array architecture for MPEG-4 image compositing and 3D rendering. The emerging MPEG4 standard for multimedia applications allows VRML-like script-based compositing of audiovisual scenes from multiple audio and visual objects. MPEG-4 supports both, natural (video) and synthetic (3D) visual objects or a combination of both. Objects can be manipulated, e.g. positioned, rotated, warped or duplicated by user interaction. A coprocessor architecture is presented, that works in parallel to an MPEG-4 video- and audio-decoder and a floating-point geometry-processor. It performs computation and bandwidth intensive low-level tasks for image compositing and rasterization. The processor consists of an SIMD array of 16 identical DSPs to reach the required processing power for real-time image warping, alphablending, z-buffering and phong-shading. The processor has an object-oriented parallel cache architecture with 2D virtual address space (e.g. textures) that allows concurrent and conflict-free access to shared image data objects for all 16 DSPs.
ASJC Scopus subject areas
- Computer Science(all)
- Computer Graphics and Computer-Aided Design
- Computer Science(all)
- Hardware and Architecture
- Engineering(all)
- Media Technology
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Proceedings : Computer Graphics International, CGI 1998. Institute of Electrical and Electronics Engineers Inc., 1998. p. 411-414 (Proceedings - Computer Graphics International, CGI 1998; Vol. 1998-January).
Research output: Chapter in book/report/conference proceeding › Conference contribution › Research › peer review
}
TY - GEN
T1 - An array processor architecture with parallel data cache for image rendering and compositing
AU - Berekovic, M.
AU - Pirsch, P.
PY - 1998
Y1 - 1998
N2 - This paper proposes a new array architecture for MPEG-4 image compositing and 3D rendering. The emerging MPEG4 standard for multimedia applications allows VRML-like script-based compositing of audiovisual scenes from multiple audio and visual objects. MPEG-4 supports both, natural (video) and synthetic (3D) visual objects or a combination of both. Objects can be manipulated, e.g. positioned, rotated, warped or duplicated by user interaction. A coprocessor architecture is presented, that works in parallel to an MPEG-4 video- and audio-decoder and a floating-point geometry-processor. It performs computation and bandwidth intensive low-level tasks for image compositing and rasterization. The processor consists of an SIMD array of 16 identical DSPs to reach the required processing power for real-time image warping, alphablending, z-buffering and phong-shading. The processor has an object-oriented parallel cache architecture with 2D virtual address space (e.g. textures) that allows concurrent and conflict-free access to shared image data objects for all 16 DSPs.
AB - This paper proposes a new array architecture for MPEG-4 image compositing and 3D rendering. The emerging MPEG4 standard for multimedia applications allows VRML-like script-based compositing of audiovisual scenes from multiple audio and visual objects. MPEG-4 supports both, natural (video) and synthetic (3D) visual objects or a combination of both. Objects can be manipulated, e.g. positioned, rotated, warped or duplicated by user interaction. A coprocessor architecture is presented, that works in parallel to an MPEG-4 video- and audio-decoder and a floating-point geometry-processor. It performs computation and bandwidth intensive low-level tasks for image compositing and rasterization. The processor consists of an SIMD array of 16 identical DSPs to reach the required processing power for real-time image warping, alphablending, z-buffering and phong-shading. The processor has an object-oriented parallel cache architecture with 2D virtual address space (e.g. textures) that allows concurrent and conflict-free access to shared image data objects for all 16 DSPs.
UR - http://www.scopus.com/inward/record.url?scp=0343730318&partnerID=8YFLogxK
U2 - 10.1109/CGI.1998.694294
DO - 10.1109/CGI.1998.694294
M3 - Conference contribution
AN - SCOPUS:0343730318
T3 - Proceedings - Computer Graphics International, CGI 1998
SP - 411
EP - 414
BT - Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 1998 Computer Graphics International, CGI 1998
Y2 - 22 June 1998 through 26 June 1998
ER -