Details
| Original language | English |
|---|---|
| Pages (from-to) | 1897-1900 |
| Number of pages | 4 |
| Journal | Proceedings - IEEE International Symposium on Circuits and Systems |
| Volume | 4 |
| Publication status | Published - 1991 |
| Event | 1991 IEEE International Symposium on Circuits and Systems Part 4 (of 5) - Singapore, Singapore Duration: 11 Jun 1991 → 14 Jun 1991 |
Abstract
An advanced defect-tolerant systolic array implementation of the 2-D convolution algorithm for real-time image processing applications is presented. The chip differs from available convolution chips in the maximum kernel size of 256 taps, the ability to convolve one video signal with up to four independent coefficient masks, support of adaptive filtering, on-chip delay lines, and implemented special processing of frame borders. Defect tolerance, e.g., reconfiguration techniques, are implemented in order to enhance yield and reliability, especially for future large area implementations.
ASJC Scopus subject areas
- Engineering(all)
- Electrical and Electronic Engineering
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In: Proceedings - IEEE International Symposium on Circuits and Systems, Vol. 4, 1991, p. 1897-1900.
Research output: Contribution to journal › Conference article › Research › peer review
}
TY - JOUR
T1 - An advanced programmable 2D-convolution chip for real time image processing
AU - Hecht, V.
AU - Ronner, K.
AU - Pirsch, P.
PY - 1991
Y1 - 1991
N2 - An advanced defect-tolerant systolic array implementation of the 2-D convolution algorithm for real-time image processing applications is presented. The chip differs from available convolution chips in the maximum kernel size of 256 taps, the ability to convolve one video signal with up to four independent coefficient masks, support of adaptive filtering, on-chip delay lines, and implemented special processing of frame borders. Defect tolerance, e.g., reconfiguration techniques, are implemented in order to enhance yield and reliability, especially for future large area implementations.
AB - An advanced defect-tolerant systolic array implementation of the 2-D convolution algorithm for real-time image processing applications is presented. The chip differs from available convolution chips in the maximum kernel size of 256 taps, the ability to convolve one video signal with up to four independent coefficient masks, support of adaptive filtering, on-chip delay lines, and implemented special processing of frame borders. Defect tolerance, e.g., reconfiguration techniques, are implemented in order to enhance yield and reliability, especially for future large area implementations.
UR - http://www.scopus.com/inward/record.url?scp=0026287601&partnerID=8YFLogxK
M3 - Conference article
AN - SCOPUS:0026287601
VL - 4
SP - 1897
EP - 1900
JO - Proceedings - IEEE International Symposium on Circuits and Systems
JF - Proceedings - IEEE International Symposium on Circuits and Systems
SN - 0271-4310
T2 - 1991 IEEE International Symposium on Circuits and Systems Part 4 (of 5)
Y2 - 11 June 1991 through 14 June 1991
ER -