Details
| Original language | English |
|---|---|
| Pages | 41-50 |
| Number of pages | 10 |
| Publication status | Published - 1995 |
| Event | 1995 IEEE Workshop on VLSI Signal Processing - Osaka, Japan Duration: 16 Oct 1995 → 18 Oct 1995 |
Conference
| Conference | 1995 IEEE Workshop on VLSI Signal Processing |
|---|---|
| Country/Territory | Japan |
| City | Osaka |
| Period | 16 Oct 1995 → 18 Oct 1995 |
Abstract
The controlling concept of a parallel homogenous SIMD video signal processor has been derived from the requirements of data dependent image processing algorithms. The processor, called HiPAR-DSP, consists of an array of 16 datapaths, local memories for each data-path, a shared memory with concurrent access in shape of a matrix and a central RISC controller. A three stage execution autonomy was implemented, consisting of conditional instructions, conditional skip of instructions by the data paths and global evaluation of local conditions by the central controller. This allows data parallel execution of data dependent medium- and high-level algorithms with very low controlling overhead. The Hi-PAR-DSP requires 300 ns to perform a tree search on a 1024 element list and 10.5 ms for the connected component labeling of a 512×512 pel image. The processor operates at a clock frequency of 100 MHz and requires a silicon area of 250 mm2 in a 0.5 μm CMOS standard cell technology.
ASJC Scopus subject areas
- Computer Science(all)
- Signal Processing
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1995. 41-50 Paper presented at 1995 IEEE Workshop on VLSI Signal Processing, Osaka, Japan.
Research output: Contribution to conference › Paper › Research › peer review
}
TY - CONF
T1 - Algorithm adapted autonomous controlling concept for a parallel single-chip digital signal processor
AU - Kneip, Johannes
AU - Wittenburg, Jens Peter
AU - Berekovic, Mladen
AU - Ronner, Karsten
AU - Pirsch, Peter
PY - 1995
Y1 - 1995
N2 - The controlling concept of a parallel homogenous SIMD video signal processor has been derived from the requirements of data dependent image processing algorithms. The processor, called HiPAR-DSP, consists of an array of 16 datapaths, local memories for each data-path, a shared memory with concurrent access in shape of a matrix and a central RISC controller. A three stage execution autonomy was implemented, consisting of conditional instructions, conditional skip of instructions by the data paths and global evaluation of local conditions by the central controller. This allows data parallel execution of data dependent medium- and high-level algorithms with very low controlling overhead. The Hi-PAR-DSP requires 300 ns to perform a tree search on a 1024 element list and 10.5 ms for the connected component labeling of a 512×512 pel image. The processor operates at a clock frequency of 100 MHz and requires a silicon area of 250 mm2 in a 0.5 μm CMOS standard cell technology.
AB - The controlling concept of a parallel homogenous SIMD video signal processor has been derived from the requirements of data dependent image processing algorithms. The processor, called HiPAR-DSP, consists of an array of 16 datapaths, local memories for each data-path, a shared memory with concurrent access in shape of a matrix and a central RISC controller. A three stage execution autonomy was implemented, consisting of conditional instructions, conditional skip of instructions by the data paths and global evaluation of local conditions by the central controller. This allows data parallel execution of data dependent medium- and high-level algorithms with very low controlling overhead. The Hi-PAR-DSP requires 300 ns to perform a tree search on a 1024 element list and 10.5 ms for the connected component labeling of a 512×512 pel image. The processor operates at a clock frequency of 100 MHz and requires a silicon area of 250 mm2 in a 0.5 μm CMOS standard cell technology.
UR - http://www.scopus.com/inward/record.url?scp=0029529683&partnerID=8YFLogxK
M3 - Paper
AN - SCOPUS:0029529683
SP - 41
EP - 50
T2 - 1995 IEEE Workshop on VLSI Signal Processing
Y2 - 16 October 1995 through 18 October 1995
ER -