Details
| Original language | English |
|---|---|
| Pages (from-to) | 163-166 |
| Number of pages | 4 |
| Journal | CIRP annals |
| Volume | 70 |
| Issue number | 1 |
| Early online date | 20 Apr 2021 |
| Publication status | Published - 2021 |
Abstract
This paper introduces a new manufacturing process for vertical interconnect accesses (VIA). In contrast to industrially established VIA metallization technologies, the presented approach takes place without any chemical plating by combining copper ink and epoxy insulator coating with CO2 laser processing for VIA drilling and copper ink sintering. The minimum VIA resistances are less than 50 mΩ, fitting the theoretically calculated value. A laboratory application scenario testing a 10 × 10 contact pad array with a pitch of 800 µm successfully demonstrates routing across five printed metallization layers, including 128 blind and 112 buried VIA.
Keywords
- Coating, Multilayer, Sintering
ASJC Scopus subject areas
- Engineering(all)
- Mechanical Engineering
- Engineering(all)
- Industrial and Manufacturing Engineering
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In: CIRP annals, Vol. 70, No. 1, 2021, p. 163-166.
Research output: Contribution to journal › Article › Research › peer review
}
TY - JOUR
T1 - Additive manufacturing of copper vertical interconnect accesses by laser processing
AU - Overmeyer, Ludger
AU - Olsen, Ejvind
AU - Hoffmann, Gerd Albert
N1 - Funding Information: The authors would like to thank the German Federal Ministry of Economics and Energy (BMWi) for funding the project “3D-CopperPrint” (20133N) and the German Research Foundation (DFG) for funding the Cluster of Excellence PhoenixD ( EXC 2122 ) based on a resolution of the German Bundestag.
PY - 2021
Y1 - 2021
N2 - This paper introduces a new manufacturing process for vertical interconnect accesses (VIA). In contrast to industrially established VIA metallization technologies, the presented approach takes place without any chemical plating by combining copper ink and epoxy insulator coating with CO2 laser processing for VIA drilling and copper ink sintering. The minimum VIA resistances are less than 50 mΩ, fitting the theoretically calculated value. A laboratory application scenario testing a 10 × 10 contact pad array with a pitch of 800 µm successfully demonstrates routing across five printed metallization layers, including 128 blind and 112 buried VIA.
AB - This paper introduces a new manufacturing process for vertical interconnect accesses (VIA). In contrast to industrially established VIA metallization technologies, the presented approach takes place without any chemical plating by combining copper ink and epoxy insulator coating with CO2 laser processing for VIA drilling and copper ink sintering. The minimum VIA resistances are less than 50 mΩ, fitting the theoretically calculated value. A laboratory application scenario testing a 10 × 10 contact pad array with a pitch of 800 µm successfully demonstrates routing across five printed metallization layers, including 128 blind and 112 buried VIA.
KW - Coating
KW - Multilayer
KW - Sintering
UR - http://www.scopus.com/inward/record.url?scp=85104582486&partnerID=8YFLogxK
U2 - 10.1016/j.cirp.2021.03.006
DO - 10.1016/j.cirp.2021.03.006
M3 - Article
AN - SCOPUS:85104582486
VL - 70
SP - 163
EP - 166
JO - CIRP annals
JF - CIRP annals
SN - 0007-8506
IS - 1
ER -