Details
| Original language | English |
|---|---|
| Pages | 27-31 |
| Number of pages | 5 |
| Publication status | Published - 2017 |
| Event | 2017Frontiers in Analog CAD, FAC 2017 - Frankfurt am Main, Germany Duration: 21 Jul 2017 → 22 Jul 2017 |
Conference
| Conference | 2017Frontiers in Analog CAD, FAC 2017 |
|---|---|
| Country/Territory | Germany |
| City | Frankfurt am Main |
| Period | 21 Jul 2017 → 22 Jul 2017 |
Abstract
With every technological achievement in electronics, new applications and concepts can be realized in circuits. One such concept is System-on-Chip (SoC) that enables developers to integrate a whole system on one physical chip. This is normally used to combine analog and digital systems. Nevertheless, prototyping such a system is resource intensive. This is caused by detailed requirements of analog components, especially nonlinear characteristics, taking the majority of computation resource. Several methods have been implemented to reduce the load, such as by changing the nonlinear behavior to a piecewise linear model and more abstract language description, e.g. SystemC instead of HDL. On the hardware perspective, runtime reduction through clock frequency scaling already reached saturation point, where any improvement only provides a marginal decrease. This and the prevalence of multi-core processors give rise to importance of parallelizing software to utilize the capabilities provided by the platform. Here we present modifications of PRAISE (Piecewise Rapid Analog Integrated Simulation Environment) to enable utilization of the multicore processors. Using the framework provided by the OpenMP library, we aim for significant runtime reduction. One of the advantages from the implementation is inherent performance increase with the number of nonlinear components, as their computation is independent from each other. The parallelism implementation will be explained and its result discussed in this paper.
ASJC Scopus subject areas
- Engineering(all)
- Electrical and Electronic Engineering
- Computer Science(all)
- Hardware and Architecture
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2017. 27-31 Paper presented at 2017Frontiers in Analog CAD, FAC 2017, Frankfurt am Main, Germany.
Research output: Contribution to conference › Paper › Research › peer review
}
TY - CONF
T1 - Accelerated Mixed-Signal Simulations Using Multi-Core Architecture
AU - Divanbeigi, Sara
AU - Aditya, Evan
AU - Olbrich, Markus
N1 - Publisher Copyright: © FAC 2017. Copyright: Copyright 2021 Elsevier B.V., All rights reserved.
PY - 2017
Y1 - 2017
N2 - With every technological achievement in electronics, new applications and concepts can be realized in circuits. One such concept is System-on-Chip (SoC) that enables developers to integrate a whole system on one physical chip. This is normally used to combine analog and digital systems. Nevertheless, prototyping such a system is resource intensive. This is caused by detailed requirements of analog components, especially nonlinear characteristics, taking the majority of computation resource. Several methods have been implemented to reduce the load, such as by changing the nonlinear behavior to a piecewise linear model and more abstract language description, e.g. SystemC instead of HDL. On the hardware perspective, runtime reduction through clock frequency scaling already reached saturation point, where any improvement only provides a marginal decrease. This and the prevalence of multi-core processors give rise to importance of parallelizing software to utilize the capabilities provided by the platform. Here we present modifications of PRAISE (Piecewise Rapid Analog Integrated Simulation Environment) to enable utilization of the multicore processors. Using the framework provided by the OpenMP library, we aim for significant runtime reduction. One of the advantages from the implementation is inherent performance increase with the number of nonlinear components, as their computation is independent from each other. The parallelism implementation will be explained and its result discussed in this paper.
AB - With every technological achievement in electronics, new applications and concepts can be realized in circuits. One such concept is System-on-Chip (SoC) that enables developers to integrate a whole system on one physical chip. This is normally used to combine analog and digital systems. Nevertheless, prototyping such a system is resource intensive. This is caused by detailed requirements of analog components, especially nonlinear characteristics, taking the majority of computation resource. Several methods have been implemented to reduce the load, such as by changing the nonlinear behavior to a piecewise linear model and more abstract language description, e.g. SystemC instead of HDL. On the hardware perspective, runtime reduction through clock frequency scaling already reached saturation point, where any improvement only provides a marginal decrease. This and the prevalence of multi-core processors give rise to importance of parallelizing software to utilize the capabilities provided by the platform. Here we present modifications of PRAISE (Piecewise Rapid Analog Integrated Simulation Environment) to enable utilization of the multicore processors. Using the framework provided by the OpenMP library, we aim for significant runtime reduction. One of the advantages from the implementation is inherent performance increase with the number of nonlinear components, as their computation is independent from each other. The parallelism implementation will be explained and its result discussed in this paper.
UR - http://www.scopus.com/inward/record.url?scp=85099576593&partnerID=8YFLogxK
M3 - Paper
AN - SCOPUS:85099576593
SP - 27
EP - 31
T2 - 2017Frontiers in Analog CAD, FAC 2017
Y2 - 21 July 2017 through 22 July 2017
ER -