Details
| Original language | English |
|---|---|
| Article number | 1257159 |
| Pages (from-to) | 409-412 |
| Number of pages | 4 |
| Journal | European Solid-State Circuits Conference |
| Publication status | Published - 2003 |
| Externally published | Yes |
| Event | 29th European Solid-State Circuits Conference, ESSCIRC 2003 - Estoril, Portugal Duration: 16 Sept 2003 → 18 Sept 2003 |
Abstract
A yield analysis of a latch-type voltage sense amplifier with a high-impedance differential input stage is presented. It quantifies the impact of supply voltage, input dc level, transistor sizing and temperature on the input offset voltage. The input dc level turns out to be most significant. Also, an analytical expression for the sensing delay is derived. Experimental results in 130nm CMOS confirm that the yield can be significantly improved by lowering the input dc voltage to about 70% of the supply voltage. Thereby, the offset standard deviation decreases from 19mV to 8.5mV without affecting the delay which is measured to be 119ps at 1.5V supply.
ASJC Scopus subject areas
- Engineering(all)
- Electrical and Electronic Engineering
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In: European Solid-State Circuits Conference, 2003, p. 409-412.
Research output: Contribution to journal › Conference article › Research › peer review
}
TY - JOUR
T1 - A yield-optimized latch-type SRAM sense amplifier
AU - Wicht, Bemhard
AU - Nirschl, Thomas
AU - Schmitt-Landsiede, Doris
PY - 2003
Y1 - 2003
N2 - A yield analysis of a latch-type voltage sense amplifier with a high-impedance differential input stage is presented. It quantifies the impact of supply voltage, input dc level, transistor sizing and temperature on the input offset voltage. The input dc level turns out to be most significant. Also, an analytical expression for the sensing delay is derived. Experimental results in 130nm CMOS confirm that the yield can be significantly improved by lowering the input dc voltage to about 70% of the supply voltage. Thereby, the offset standard deviation decreases from 19mV to 8.5mV without affecting the delay which is measured to be 119ps at 1.5V supply.
AB - A yield analysis of a latch-type voltage sense amplifier with a high-impedance differential input stage is presented. It quantifies the impact of supply voltage, input dc level, transistor sizing and temperature on the input offset voltage. The input dc level turns out to be most significant. Also, an analytical expression for the sensing delay is derived. Experimental results in 130nm CMOS confirm that the yield can be significantly improved by lowering the input dc voltage to about 70% of the supply voltage. Thereby, the offset standard deviation decreases from 19mV to 8.5mV without affecting the delay which is measured to be 119ps at 1.5V supply.
UR - http://www.scopus.com/inward/record.url?scp=84881282628&partnerID=8YFLogxK
U2 - 10.1109/ESSCIRC.2003.1257159
DO - 10.1109/ESSCIRC.2003.1257159
M3 - Conference article
AN - SCOPUS:84881282628
SP - 409
EP - 412
JO - European Solid-State Circuits Conference
JF - European Solid-State Circuits Conference
SN - 1930-8833
M1 - 1257159
T2 - 29th European Solid-State Circuits Conference, ESSCIRC 2003
Y2 - 16 September 2003 through 18 September 2003
ER -