Details
| Original language | English |
|---|---|
| Title of host publication | 1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992 |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 1685-1688 |
| Number of pages | 4 |
| ISBN (electronic) | 0780305930 |
| Publication status | Published - 1992 |
| Event | 1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992 - San Diego, United States Duration: 10 May 1992 → 13 May 1992 |
Publication series
| Name | Proceedings - IEEE International Symposium on Circuits and Systems |
|---|---|
| Volume | 4 |
| ISSN (Print) | 0271-4310 |
Abstract
This paper discusses a VLSI based multiprocessor architecture for real-time processing of video coding applications. The architecture consists of multiple identical processing elements and is characterized as MIMD (Multiple Instruction Multiple Data). The architecture of a processing element is based on a standard processor core, e. g. a RISC processor, and a low level coprocessor. The low level coprocessor is adapted to parallel processing of convolution-like operations. The performance of the architecture is discussed withrespectto the processing time for hybrid coding algorithms as well as to the required silicon area.
ASJC Scopus subject areas
- Engineering(all)
- Electrical and Electronic Engineering
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1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992. Institute of Electrical and Electronics Engineers Inc., 1992. p. 1685-1688 230352 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 4).
Research output: Chapter in book/report/conference proceeding › Conference contribution › Research › peer review
}
TY - GEN
T1 - A VLSI based multiprocessor architecture for video signal processing
AU - Jeschke, Hartwig
AU - Gaedke, Klaus
AU - Pirsch, Peter
PY - 1992
Y1 - 1992
N2 - This paper discusses a VLSI based multiprocessor architecture for real-time processing of video coding applications. The architecture consists of multiple identical processing elements and is characterized as MIMD (Multiple Instruction Multiple Data). The architecture of a processing element is based on a standard processor core, e. g. a RISC processor, and a low level coprocessor. The low level coprocessor is adapted to parallel processing of convolution-like operations. The performance of the architecture is discussed withrespectto the processing time for hybrid coding algorithms as well as to the required silicon area.
AB - This paper discusses a VLSI based multiprocessor architecture for real-time processing of video coding applications. The architecture consists of multiple identical processing elements and is characterized as MIMD (Multiple Instruction Multiple Data). The architecture of a processing element is based on a standard processor core, e. g. a RISC processor, and a low level coprocessor. The low level coprocessor is adapted to parallel processing of convolution-like operations. The performance of the architecture is discussed withrespectto the processing time for hybrid coding algorithms as well as to the required silicon area.
UR - http://www.scopus.com/inward/record.url?scp=84959165570&partnerID=8YFLogxK
U2 - 10.1109/ISCAS.1992.230352
DO - 10.1109/ISCAS.1992.230352
M3 - Conference contribution
AN - SCOPUS:84959165570
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
SP - 1685
EP - 1688
BT - 1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992
Y2 - 10 May 1992 through 13 May 1992
ER -