Details
| Original language | English |
|---|---|
| Pages (from-to) | 159-169 |
| Number of pages | 11 |
| Journal | Journal of VLSI Signal Processing |
| Volume | 5 |
| Issue number | 2-3 |
| Publication status | Published - 1 Apr 1993 |
Abstract
A MIMD based multiprocessor architecture for real-time video processing applications consisting of identical bus connected processing elements has been developed. Each processing element contains a RISC processor for controlling and data-dependent tasks and a Low Level Coprocessor for fast processing of convolution-type video processing tasks. To achieve efficient parallel processing of video input signals, the architecture supports independent processing of overlapping image segments. Running at a clock rate of 40 MHz, a single processing element provides a peak performance of 640 Mega arithmetic operations per second (MOPS). For the real-time processing of basic video processing tasks like 3×3 FIR-filter, 8×8 2D-DCT and motion estimation, a single processing element provides a sufficient computational rate for video signals with Common Intermediate Format (CIF) at a frame rate up to 30 Hz. For hybrid source coding of CIF video signals at a frame rate of 30 Hz a multiprocessor system consisting of six processing elements is required. A linear speedup of the multiprocessor system compared to a single processing element is achieved. A VLSI implementation of a processing element in 0.8 μm CMOS technology is under development.
ASJC Scopus subject areas
- Computer Science(all)
- Signal Processing
- Computer Science(all)
- Information Systems
- Engineering(all)
- Electrical and Electronic Engineering
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In: Journal of VLSI Signal Processing, Vol. 5, No. 2-3, 01.04.1993, p. 159-169.
Research output: Contribution to journal › Article › Research › peer review
}
TY - JOUR
T1 - A VLSI based MIMD architecture of a multiprocessor system for real-time video processing applications
AU - Gaedke, Klaus
AU - Jeschke, Hartwig
AU - Pirsch, Peter
PY - 1993/4/1
Y1 - 1993/4/1
N2 - A MIMD based multiprocessor architecture for real-time video processing applications consisting of identical bus connected processing elements has been developed. Each processing element contains a RISC processor for controlling and data-dependent tasks and a Low Level Coprocessor for fast processing of convolution-type video processing tasks. To achieve efficient parallel processing of video input signals, the architecture supports independent processing of overlapping image segments. Running at a clock rate of 40 MHz, a single processing element provides a peak performance of 640 Mega arithmetic operations per second (MOPS). For the real-time processing of basic video processing tasks like 3×3 FIR-filter, 8×8 2D-DCT and motion estimation, a single processing element provides a sufficient computational rate for video signals with Common Intermediate Format (CIF) at a frame rate up to 30 Hz. For hybrid source coding of CIF video signals at a frame rate of 30 Hz a multiprocessor system consisting of six processing elements is required. A linear speedup of the multiprocessor system compared to a single processing element is achieved. A VLSI implementation of a processing element in 0.8 μm CMOS technology is under development.
AB - A MIMD based multiprocessor architecture for real-time video processing applications consisting of identical bus connected processing elements has been developed. Each processing element contains a RISC processor for controlling and data-dependent tasks and a Low Level Coprocessor for fast processing of convolution-type video processing tasks. To achieve efficient parallel processing of video input signals, the architecture supports independent processing of overlapping image segments. Running at a clock rate of 40 MHz, a single processing element provides a peak performance of 640 Mega arithmetic operations per second (MOPS). For the real-time processing of basic video processing tasks like 3×3 FIR-filter, 8×8 2D-DCT and motion estimation, a single processing element provides a sufficient computational rate for video signals with Common Intermediate Format (CIF) at a frame rate up to 30 Hz. For hybrid source coding of CIF video signals at a frame rate of 30 Hz a multiprocessor system consisting of six processing elements is required. A linear speedup of the multiprocessor system compared to a single processing element is achieved. A VLSI implementation of a processing element in 0.8 μm CMOS technology is under development.
UR - http://www.scopus.com/inward/record.url?scp=0027574931&partnerID=8YFLogxK
U2 - 10.1007/BF01581293
DO - 10.1007/BF01581293
M3 - Article
AN - SCOPUS:0027574931
VL - 5
SP - 159
EP - 169
JO - Journal of VLSI Signal Processing
JF - Journal of VLSI Signal Processing
SN - 0922-5773
IS - 2-3
ER -