Details
| Original language | English |
|---|---|
| Pages (from-to) | 781-791 |
| Number of pages | 11 |
| Journal | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
| Volume | 16 |
| Issue number | 7 |
| Publication status | Published - Jul 2008 |
| Externally published | Yes |
Abstract
A novel implementation of a tag sorting circuit for a weighted fair queueing (WFQ) enabled Internet Protocol (IP) packet scheduler is presented. The design consists of a search tree, matching circuitry, and a custom memory layout. It is implemented using 130-nm silicon technology and supports quality of service (QoS) on networks at line speeds of 40 Gb/s, enabling next generation IP services to be deployed.
Keywords
- Internet packet scheduling, Lookup, quality of service (QoS), Time-stamp sorting, Traffic management, Weighted fair queueing (WFQ)
ASJC Scopus subject areas
- Computer Science(all)
- Software
- Computer Science(all)
- Hardware and Architecture
- Engineering(all)
- Electrical and Electronic Engineering
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In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 16, No. 7, 07.2008, p. 781-791.
Research output: Contribution to journal › Article › Research › peer review
}
TY - JOUR
T1 - A Scalable Packet Sorting Circuit for High-Speed WFQ Packet Scheduling
AU - McLaughlin, K.
AU - Sezer, S.
AU - Blume, H.
AU - Yang, X.
AU - Kupzog, F.
AU - Noll, T.
N1 - Funding information: Manuscript received April 1, 2007; revised July 3, 2007. This work was supported by Invest Northern Ireland and the Department for Employment and Learning. It is protected by Patent No. 0524845.
PY - 2008/7
Y1 - 2008/7
N2 - A novel implementation of a tag sorting circuit for a weighted fair queueing (WFQ) enabled Internet Protocol (IP) packet scheduler is presented. The design consists of a search tree, matching circuitry, and a custom memory layout. It is implemented using 130-nm silicon technology and supports quality of service (QoS) on networks at line speeds of 40 Gb/s, enabling next generation IP services to be deployed.
AB - A novel implementation of a tag sorting circuit for a weighted fair queueing (WFQ) enabled Internet Protocol (IP) packet scheduler is presented. The design consists of a search tree, matching circuitry, and a custom memory layout. It is implemented using 130-nm silicon technology and supports quality of service (QoS) on networks at line speeds of 40 Gb/s, enabling next generation IP services to be deployed.
KW - Internet packet scheduling
KW - Lookup, quality of service (QoS)
KW - Time-stamp sorting
KW - Traffic management
KW - Weighted fair queueing (WFQ)
UR - http://www.scopus.com/inward/record.url?scp=48149099928&partnerID=8YFLogxK
U2 - 10.1109/TVLSI.2008.2000323
DO - 10.1109/TVLSI.2008.2000323
M3 - Article
AN - SCOPUS:48149099928
VL - 16
SP - 781
EP - 791
JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SN - 1063-8210
IS - 7
ER -