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| Original language | English |
|---|---|
| Journal | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
| Publication status | Published - 2008 |
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A scalable packet sorting circuit for high-speed WFQ packet scheduling. / McLaughlin, K.; Sezer, S.; Blume, H. et al.
In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2008.
In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2008.
Research output: Contribution to journal › Article › Research › peer review
McLaughlin, K, Sezer, S, Blume, H, Yang, X, Kupzog, F & Noll, T 2008, 'A scalable packet sorting circuit for high-speed WFQ packet scheduling', IEEE Transactions on Very Large Scale Integration (VLSI) Systems. https://doi.org/10.1109/TVLSI.2008.2000323
McLaughlin, K., Sezer, S., Blume, H., Yang, X., Kupzog, F., & Noll, T. (2008). A scalable packet sorting circuit for high-speed WFQ packet scheduling. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. https://doi.org/10.1109/TVLSI.2008.2000323
McLaughlin K, Sezer S, Blume H, Yang X, Kupzog F, Noll T. A scalable packet sorting circuit for high-speed WFQ packet scheduling. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2008. doi: 10.1109/TVLSI.2008.2000323
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